Journals in DBLP

J. Electronic Testing
2005, volume: 21, number: 2

1. Vishwani D. Agrawal
   Editorial. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:111- [Journal]
   
2. Bruce C. Kim
   Test Technology Technical Council Newsletter. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:113-114 [Journal]
   
3. Anand L. D'Souza, Michael S. Hsiao
   Error Diagnosis of Sequential Circuits Using Region-Based Model. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:115-126 [Journal]
   
4. Yvan Maidon, Thomas Zimmer, André Ivanov
   An Analog Circuit Fault Characterization Methodology. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:127-134 [Journal]
   
5. Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
   Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:135-146 [Journal]
   
6. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
   Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:147-159 [Journal]
   
7. Dimitri Kagaris
   Phase Shifter Merging. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:161-168 [Journal]
   
8. Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
   Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:169-179 [Journal]
   
9. Huawei Li, Xiaowei Li
   Selection of Crosstalk-Induced Faults in Enhanced Delay Test. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:2, pp:181-195 [Journal]