Journals in DBLP

J. Electronic Testing
2005, volume: 21, number: 1

1. Vishwani D. Agrawal
   Editorial. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:5- [Journal]
   
2. Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell
   A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:9-16 [Journal]
   
3. Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
   Optimal Interconnect ATPG Under a Ground-Bounce Constraint. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:17-31 [Journal]
   
4. Jean Michel Portal, H. Aziza, Didier Née
   EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:33-42 [Journal]
   
5. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
   Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:43-55 [Journal]
   
6. Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
   Modeling Feedback Bridging Faults with Non-Zero Resistance. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:57-69 [Journal]
   
7. Jaan Raik, Tanel Nõmmeots, Raimund Ubar
   A New Testability Calculation Method to Guide RTL Test Generation. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:71-82 [Journal]
   
8. Biplab K. Sikdar, Samir Roy, Debesh K. Das
   A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:83-93 [Journal]
   
9. Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri
   Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2005, v:21, n:1, pp:95-107 [Journal]