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Journals in DBLP

J. Electronic Testing
2006, volume: 22, number: 4-6

  1. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:307- [Journal]
  2. Salvador Mir, Tim Cheng, Andrew Richardson
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:311- [Journal]
  3. Carsten Wegener, Michael Peter Kennedy
    Test Development Through Defect and Test Escape Level Estimation for Data Converters. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:313-324 [Journal]
  4. Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro
    A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:325-335 [Journal]
  5. Heinz Mattes, Stéphane Kirmser, Sebastian Sattler
    Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:337-350 [Journal]
  6. Vincent Kerzerho, Serge Bernard, Philippe Cauvet, J. M. Janik
    A First Step for an INL Spectral-Based BIST: The Memory Optimization. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:351-357 [Journal]
  7. K. Georgopoulos, A. Lechner, M. Burbidge, A. Richardson
    Investigation into the Use of Hybrid Solutions for SigmaDelta A/D Converter Testing. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:359-370 [Journal]
  8. Tejasvi Das, Anand Gopalan, Clyde Washburn, P. R. Mukund
    Towards Fault-Tolerant RF Front Ends. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:371-386 [Journal]
  9. Jiun-Lang Huang
    On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:387-398 [Journal]
  10. Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud
    Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:399-409 [Journal]
  11. Yukiya Miura
    Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:411-423 [Journal]
  12. Michel Morneau, Abdelhakim Khouas
    TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:425-436 [Journal]
  13. Miguel Angel Domínguez, José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli
    A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:437-448 [Journal]
  14. Amit Laknaur, Sai Raghuram Durbha, Haibo Wang
    Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:449-462 [Journal]
  15. V. Loukusa
    Embedded System Level Self-Test for Mixed-Signal IO Verification. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:463-470 [Journal]
  16. Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee
    Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:471-482 [Journal]
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