Journals in DBLP
Vishwani D. Agrawal Editorial. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:5- [Journal ] Bashir M. Al-Hashimi , Dimitris Gizopoulos , Manoj Sachdev , Adit D. Singh New JETTA Editors, 2006. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:9-10 [Journal ] Ali Chehab , Saurabh Patel , Rafic Z. Makki Scaling of iDDT Test Methods for Random Logic Circuits. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:11-22 [Journal ] Audhild Vaaje Theorems for Fault Collapsing in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:23-36 [Journal ] Sunghoon Chun , Sangwook Kim , Hong-Sik Kim , Sungho Kang An Efficient Dictionary Organization for Maximum Diagnosis. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:37-48 [Journal ] Zhen Shi , Peter Sandborn Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:49-60 [Journal ] Piet Engelke , Ilia Polian , Michel Renovell , Bernd Becker Automatic Test Pattern Generation for Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:61-69 [Journal ] Hani Rizk , Christos A. Papachristou , Francis G. Wolff A Self Test Program Design Technique for Embedded DSP Cores. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:71-87 [Journal ] Yannick Bonhomme , Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel A Gated Clock Scheme for Low Power Testing of Logic Cores. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:89-99 [Journal ] Vitalij Ocheretnij , Michael Gössel , Egor S. Sogomonyan , Daniel Marienfeld Modulo p =3 Checking for a Carry Select Adder. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2006, v:22, n:1, pp:101-107 [Journal ]