Journals in DBLP

J. Electronic Testing
2006, volume: 22, number: 2

1. Vishwani D. Agrawal
   Editorial. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:111- [Journal]
   
2. Bipul C. Paul, Kaushik Roy
   Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:115-124 [Journal]
   
3. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
   Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:125-142 [Journal]
   
4. Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
   Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2^m). [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:143-150 [Journal]
   
5. Yu-Chiun Lin, Shi-Yu Huang
   Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:151-159 [Journal]
   
6. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
   An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:161-172 [Journal]
   
7. Zemo Yang, Samiha Mourad
   Crosstalk Induced Fault Analysis and Test in DRAMs. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:173-187 [Journal]
   
8. N. Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet
   Electro-thermal Stimuli for MEMS Testing in FSBM Technology. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:189-198 [Journal]
   
9. Fei Su, Sule Ozev, Krishnendu Chakrabarty
   Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2006, v:22, n:2, pp:199-210 [Journal]