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Journals in DBLP
- Vishwani D. Agrawal
Editorial. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:111- [Journal]
- Bruce Kim
Test Technology Newsletter April 2007. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:113-114 [Journal]
- Mohammad Tehranipoor
Guest Editorial. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:115-116 [Journal]
- Tad Hogg, Greg Snider
Defect-tolerant Logic with Nanoscale Crossbar Circuits. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:117-129 [Journal]
- Jason G. Brown, R. D. (Shawn) Blanton
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:131-144 [Journal]
- Zhanglei Wang, Krishnendu Chakrabarty
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:145-161 [Journal]
- Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi
On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:163-174 [Journal]
- Jia Di, Parag K. Lala
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:175-192 [Journal]
- Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli
QCA Circuits for Robust Coplanar Crossing. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:193-210 [Journal]
- Mo Liu, Craig S. Lent
Reliability and Defect Tolerance in Metallic Quantum-dot Cellular Automata. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:211-218 [Journal]
- Fei Su, William L. Hwang, Arindam Mukherjee, Krishnendu Chakrabarty
Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:219-233 [Journal]
- Wenjing Rao, Alex Orailoglu, Ramesh Karri
Towards Nanoelectronics Processor Architectures. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:235-254 [Journal]
- Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Designing Nanoscale Logic Circuits Based on Markov Random Fields. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2007, v:23, n:2-3, pp:255-266 [Journal]
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