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Journals in DBLP

Computer Architecture Letters
2006, volume: 5, number: 2


  1. An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation. [Citation Graph (, )][DBLP]


  2. A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator. [Citation Graph (, )][DBLP]


  3. User-Driven Frequency Scaling. [Citation Graph (, )][DBLP]


  4. Disintermediated Active Communication. [Citation Graph (, )][DBLP]


  5. Foreword. [Citation Graph (, )][DBLP]


  6. Exploiting Narrow Values for Soft Error Tolerance. [Citation Graph (, )][DBLP]


  7. Subtleties of Transactional Memory Atomicity Semantics. [Citation Graph (, )][DBLP]


  8. A Case for Compressing Traces with BDDs. [Citation Graph (, )][DBLP]

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