Journals in DBLP

Computer Architecture Letters
2007, volume: 6, number: 1

1. 
   Explaining Dynamic Cache Partitioning Speed Ups. [Citation Graph (, )][DBLP]
   
   
2. 
   Circuit-Switched Coherence. [Citation Graph (, )][DBLP]
   
   
3. 
   CIM: A Reliable Metric for Evaluating Program Phase Classifications. [Citation Graph (, )][DBLP]
   
   
4. 
   Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy. [Citation Graph (, )][DBLP]
   
   
5. 
   Probabilistic Prediction of Temporal Locality. [Citation Graph (, )][DBLP]
   
   
6. 
   Nahalal: Cache Organization for Chip Multiprocessors. [Citation Graph (, )][DBLP]