Journals in DBLP

IEEE Design & Test of Computers
2007, volume: 24, number: 5

1. 
   Combining synchronous and asynchronous timing schemes for high-performance systems. [Citation Graph (, )][DBLP]
   
   
2. 
   Guest Editors' Introduction: GALS Design and Validation. [Citation Graph (, )][DBLP]
   
   
3. 
   A Survey and Taxonomy of GALS Design Styles. [Citation Graph (, )][DBLP]
   
   
4. 
   Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. [Citation Graph (, )][DBLP]
   
   
5. 
   Adaptive Latency-Insensitive Protocols. [Citation Graph (, )][DBLP]
   
   
6. 
   A GALS Infrastructure for a Massively Parallel Multiprocessor. [Citation Graph (, )][DBLP]
   
   
7. 
   A Highly Scalable GALS Crossbar Using Token Ring Arbitration. [Citation Graph (, )][DBLP]
   
   
8. 
   Guest Editor's Introduction: Getting More Out of Test. [Citation Graph (, )][DBLP]
   
   
9. 
   X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. [Citation Graph (, )][DBLP]
   
   
10. 
    Cell Broadband Engine Debugging for Unknown Events. [Citation Graph (, )][DBLP]
    
    
11. 
    The Psychology of Electronic Test. [Citation Graph (, )][DBLP]
    
    
12. 
    DAC Highlights. [Citation Graph (, )][DBLP]
    
    
13. 
    DATC Newsletter. [Citation Graph (, )][DBLP]
    
    
14. 
    Book Reviews: Test Tutorials in Book Form. [Citation Graph (, )][DBLP]
    
    
15. 
    DATE 07 workshop on diagnostic services in NoCs. [Citation Graph (, )][DBLP]
    
    
16. 
    TTTC Newsletter. [Citation Graph (, )][DBLP]
    
    
17. 
    ITC exhibits for fun and profit. [Citation Graph (, )][DBLP]