Journals in DBLP

IEEE Design & Test of Computers
2009, volume: 26, number: 5

1. 
   Stacking chips in 3D. [Citation Graph (, )][DBLP]
   
   
2. 
   Guest Editors' Introduction: Opportunities and Challenges of 3D Integration. [Citation Graph (, )][DBLP]
   
   
3. 
   Opportunities and Challenges for 3D Systems and Their Design. [Citation Graph (, )][DBLP]
   
   
4. 
   Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity. [Citation Graph (, )][DBLP]
   
   
5. 
   Test Challenges for 3D Integrated Circuits. [Citation Graph (, )][DBLP]
   
   
6. 
   3D DRAM Design and Application to 3D Multicore Systems. [Citation Graph (, )][DBLP]
   
   
7. 
   Mixed-Signal Production Test: A Measurement Principle Perspective. [Citation Graph (, )][DBLP]
   
   
8. 
   Statistics in Semiconductor Test: Going beyond Yield. [Citation Graph (, )][DBLP]
   
   
9. 
   Multidimensional Test Escape Rate Modeling. [Citation Graph (, )][DBLP]
   
   
10. 
    A Generic Virtual Bus for Hardware Simulator Composition. [Citation Graph (, )][DBLP]
    
    
11. 
    Robust On-Chip Signaling by Staggered and Twisted Bundle. [Citation Graph (, )][DBLP]
    
    
12. 
    Test Technology TC Newsletter. [Citation Graph (, )][DBLP]
    
    
13. 
    Teaching someone to fish. [Citation Graph (, )][DBLP]
    
    
14. 
    CEDA Currents. [Citation Graph (, )][DBLP]
    
    
15. 
    Design Automation Technical Committee Newsletter. [Citation Graph (, )][DBLP]
    
    
16. 
    The fate of stacking. [Citation Graph (, )][DBLP]