The SCEAS System | ||||
Paper infoJean-Claude Klein, François Collange, M. BilodeauA Bit Plane Architecture For An Image Analysis Processor Implemented With P.L.C.A. Gate Array. [Citation Graph (0, 0)][DBLP] ECCV, 1990, pp:33-49 [Conf] Scores and Rank SCEAS: 0.41721 SCEAS_PS: 0 SCEAS_BPS: 0 SCEAS_EPS: 0 SCEAS_BEPS: 0 SCEAS_B0: 3.11202 PAGE_RANK: 0.48050 HITS_H: 0 HITS_A: 0 BHITS_H: 0 BHITS_A: 0 SALSA_A: 0 SALSA_H: 0 BSALSA_A: 0 BSALSA_H: 0 P: 0 BCC: 0 citations_to_me: 0 citations_from_me: 0 Graph produced by graphviz-1.8.5 | ||||
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System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |