The SCEAS System | ||||
Paper infoDac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. WendelKey features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:871-878 [Conf] Scores and Rank SCEAS: 0.41721 SCEAS_PS: 0 SCEAS_BPS: 0 SCEAS_EPS: 0 SCEAS_BEPS: 0 SCEAS_B0: 3.11202 PAGE_RANK: 0.48050 HITS_H: 0 HITS_A: 0 BHITS_H: 0 BHITS_A: 0 SALSA_A: 0 SALSA_H: 0 BSALSA_A: 0 BSALSA_H: 0 P: 0 BCC: 0 citations_to_me: 0 citations_from_me: 0 Graph produced by graphviz-1.8.5 | ||||
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