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Paper info

Kaijie Wu, Ramesh Karri
Fault secure datapath synthesis using hybrid time and hardware redundancy. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1476-1485 [Journal]

Scores and Rank
SCEAS: 0.41721
SCEAS_PS: 0
SCEAS_BPS: 0
SCEAS_EPS: 0
SCEAS_BEPS: 0
SCEAS_B0: 3.11202
PAGE_RANK: 0.48050
HITS_H: 0
HITS_A: 0
BHITS_H: 0
BHITS_A: 0
SALSA_A: 0
SALSA_H: 0
BSALSA_A: 0
BSALSA_H: 0
P: 0
BCC: 0
citations_to_me: 0
citations_from_me: 0



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NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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