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Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. [Citation Graph (0, 0)][DBLP]
FPL, 2006, pp:1-6 [Conf]

Scores and Rank
SCEAS: 0.41721
SCEAS_PS: 0
SCEAS_BPS: 0
SCEAS_EPS: 0
SCEAS_BEPS: 0
SCEAS_B0: 3.11202
PAGE_RANK: 0.48050
HITS_H: 0
HITS_A: 0
BHITS_H: 0
BHITS_A: 0
SALSA_A: 0
SALSA_H: 0
BSALSA_A: 0
BSALSA_H: 0
P: 0
BCC: 0
citations_to_me: 0
citations_from_me: 0



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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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