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## Search the dblp DataBase
Kiyoshi Oguri:
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## Publications of Author- Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya
**Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA.**[Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2003, pp:54-68 [Conf] - Norbert Imlig, Ryusuke Konishi, Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Minoru Inamori, Hiroshi Nakada
**Communicating logic: an alternative embedded stream processing paradigm.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:317-322 [Conf] - Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri
**PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI.**[Citation Graph (0, 0)][DBLP] ASYNC, 2001, pp:54-0 [Conf] - Shinya Kyusaka, Hayato Higuchi, Taichi Nagamoto, Yuichiro Shibata, Kiyoshi Oguri
**Evaluation of Space Allocation Circuits.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:428-437 [Conf] - Taichi Nagamoto, Satoshi Yano, Mitsuru Uchida, Yuichiro Shibata, Kiyoshi Oguri
**New Area Management Method Based on "Pressure" for Plastic Cell Architecture.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:418-427 [Conf] - Kouichi Nagami, Kiyoshi Oguri, Tsunemichi Shiozawa, Hideyuki Ito, Ryusuke Konishi
**Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose.**[Citation Graph (0, 0)][DBLP] FCCM, 1998, pp:68-77 [Conf] - Takehiro Ito, Yuichiro Shibata, Kiyoshi Oguri
**Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA.**[Citation Graph (0, 0)][DBLP] FPL, 2004, pp:911-916 [Conf] - Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri
**Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA.**[Citation Graph (0, 0)][DBLP] FPL, 2005, pp:666-669 [Conf] - Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada
**An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture.**[Citation Graph (0, 0)][DBLP] FPL, 2000, pp:805-809 [Conf] - Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Ryusuke Konishi, Norbert Imlig
**A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI Architecture.**[Citation Graph (0, 0)][DBLP] FPL, 1998, pp:426-430 [Conf] - Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura
**Multi-Level Optimization for Large Scale ASICS.**[Citation Graph (0, 0)][DBLP] ICCAD, 1990, pp:564-567 [Conf] - Kiyoshi Oguri, Norbert Imlig, Hideyuki Ito, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa
**General-Purpose Computer Architecture Based on Fully Programmable Logic.**[Citation Graph (0, 0)][DBLP] ICES, 1998, pp:323-334 [Conf] - Hiroshi Nakada, Kiyoshi Oguri, Norbert Imlig, Minoru Inamori, Ryusuke Konishi, Hideyuki Ito, Kouichi Nagami, Tsunemichi Shiozawa
**Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer.**[Citation Graph (0, 0)][DBLP] IPPS/SPDP Workshops, 1999, pp:679-687 [Conf] - Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig
**Self-reorganising systems on VLSI circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:310-313 [Conf] - Hideyuki Ito, Kiyoshi Oguri, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa
**The Plastic Cell Architecture for Dynamic Reconfigurable Computing.**[Citation Graph (0, 0)][DBLP] International Workshop on Rapid System Prototyping, 1998, pp:39-44 [Conf] - Hiroyuki Yamashita, Toshihiko Suguri, Shingo Kinoshita, Yasushi Okada, Kiyoshi Oguri
**Message routing latency-minimizing method in an ASIC design for distributed cooperative communication protocol processing.**[Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 1998, v:29, n:3, pp:39-58 [Journal] - Miwa Miyata, Hideyuki Tsuchiya, Yuichiro Shibata, Kiyoshi Oguri
**An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor.**[Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-4 [Conf] **Bayesian Multi-topic Microarray Analysis with Hyperparameter Reestimation.**[Citation Graph (, )][DBLP]**Dynamic hyperparameter optimization for bayesian topical trend analysis.**[Citation Graph (, )][DBLP]**Retrieving 3-d information with FPGA-based stream processing.**[Citation Graph (, )][DBLP]**Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine.**[Citation Graph (, )][DBLP]**A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator.**[Citation Graph (, )][DBLP]**An optimization method of DMA transfer for a general purpose reconfigurable machine.**[Citation Graph (, )][DBLP]**Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator.**[Citation Graph (, )][DBLP]**Accelerating Collapsed Variational Bayesian Inference for Latent Dirichlet Allocation with Nvidia CUDA Compatible Devices.**[Citation Graph (, )][DBLP]**Modeling Topical Trends over Continuous Time with Priors.**[Citation Graph (, )][DBLP]**Bag of Timestamps: A Simple and Efficient Bayesian Chronological Mining.**[Citation Graph (, )][DBLP]**Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator.**[Citation Graph (, )][DBLP]**A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA.**[Citation Graph (, )][DBLP]
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