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Publications of Author

1. Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya
   Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. [Citation Graph (0, 0)][DBLP]
   Asia-Pacific Computer Systems Architecture Conference, 2003, pp:54-68 [Conf]
   
2. Hidehisa Nagano, Takayuki Suyama, Akira Nagoya
   Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1999, pp:161-164 [Conf]
   
3. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
   An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:253-258 [Conf]
   
4. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
   New Methods to Find Optimal Non-Disjoint Bi-Decompositions. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1998, pp:59-68 [Conf]
   
5. Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri
   PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:54-0 [Conf]
   
6. Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya
   A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. [Citation Graph (0, 0)][DBLP]
   CODES, 1997, pp:147-152 [Conf]
   
7. Takayuki Suyama, Makoto Yokoo, Akira Nagoya
   Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation. [Citation Graph (0, 0)][DBLP]
   CP, 1999, pp:434-445 [Conf]
   
8. Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
   Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:755-0 [Conf]
   
9. Akihiro Matsuura, Hidehisa Nagano, Akira Nagoya
   A Method for Implementing Fractal Image Compression on Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
   FPGA, 1999, pp:251- [Conf]
   
10. Hidehisa Nagano, Takayuki Suyama, Akira Nagoya
    Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:261- [Conf]
    
11. Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima
    A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:665-674 [Conf]
    
12. Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada
    An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:805-809 [Conf]
    
13. Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
    Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:39-44 [Conf]
    
14. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
    An Integrated Approach for Synthesizing LUT Networks. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:136-139 [Conf]
    
15. Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura
    Multi-Level Optimization for Large Scale ASICS. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:564-567 [Conf]
    
16. Hiroshi Sawada, Takayuki Suyama, Akira Nagoya
    Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:353-358 [Conf]
    
17. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
    A new method to express functional permissibilities for LUT based FPGAs and its applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:254-261 [Conf]
    
18. Norbert Imlig, Tsunemichi Shiozawa, Kouichi Nagami, Yoshiki Nakane, Ryusuke Konishi, Hideyuki Ito, Akira Nagoya
    Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:142- [Conf]
    
19. Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya
    An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:670-678 [Conf]
    
20. Takayuki Suyama, Makoto Yokoo, Akira Nagoya
    Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:709-711 [Conf]
    
21. Kaihiro Matsuura, Akira Nagoya
    Formulation of the Addition-Shift-Sequence Problem and Its Complexity. [Citation Graph (0, 0)][DBLP]
    ISAAC, 1997, pp:42-51 [Conf]
    
22. Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig
    Self-reorganising systems on VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:310-313 [Conf]
    
23. Akihiro Matsuura, Akira Nagoya
    Summation Algorithms on Constrained Reconfigurable Meshes. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1999, pp:400-405 [Conf]
    
24. Takayuki Suyama, Hiroshi Sawada, Akira Nagoya
    LUT-based FPGA Technology Mapping using Permissible Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:215-218 [Conf]
    
25. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
    SPFD: A new method to express functional flexibility. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:840-849 [Journal]
    
26. Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada, Akira Nagoya
    Solving satisfiability problems using reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:109-116 [Journal]