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Ron Sass: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Keith D. Underwood, Ron Sass, Walter B. Ligon III
    A Reconfigurable Extension to the Network Interface of Beowulf Clusters. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2001, pp:212-0 [Conf]
  2. David L. Andrews, Ron Sass, Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp
    The Case for High Level Programming Models for Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:21-32 [Conf]
  3. Jeff Young, Ron Sass
    FERP Interface and Interconnect Cores for Stream Processing Applications. [Citation Graph (0, 0)][DBLP]
    EUC, 2004, pp:291-300 [Conf]
  4. Brian Greskamp, Ron Sass
    A Virtual Machine for Merit-Based Runtime Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:287-288 [Conf]
  5. Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David L. Andrews
    Enabling a Uniform Programming Model Across the Software/Hardware Boundary. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:89-98 [Conf]
  6. Brian Leonard, Jeff Young, Ron Sass
    Online placement infrastructure to support run-time reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:256- [Conf]
  7. Ranjesh G. Jaganathan, Matthew Simpson, Ron Sass
    Automatic discovery, selection, and specialization of modules in RCADE. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:256- [Conf]
  8. Nathan DeBardeleben, Walter B. Ligon III, Ron Sass
    Arches: An Infrastructure for PSE Development. [Citation Graph (0, 0)][DBLP]
    HIPS, 2004, pp:120-128 [Conf]
  9. Ron Sass, Matt W. Mutka
    Transformations on Doubly Nested Loops. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:343-346 [Conf]
  10. Marwan Krunz, Ron Sass, Herman D. Hughes
    Statistical Characteristics and Multiplexing of MPEG Streams. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1995, pp:455-462 [Conf]
  11. Nathan DeBardeleben, Walter B. Ligon III, Ron Sass
    Arches: An Infrastructure for PSE Development. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:120-128 [Conf]
  12. Shyamnath Harinath, Ron Sass
    Reconfigurable Mapping Functions for Online Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:173- [Conf]
  13. Krishna Muriki, Keith D. Underwood, Ron Sass
    RC-BLAST: Towards a Portable, Cost-Effective Open Source Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  14. Pradeep Nalabalapu, Ron Sass
    Bandwidth Management with a Reconfigurable Data Cache. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  15. Chi-Ming Chiang, Qiang Du, Matt W. Mutka, Ron Sass
    An Empirical Study of Scalable Domain Decomposition Methods for a 2-D Parabolic Equation Solver. [Citation Graph (0, 0)][DBLP]
    PPSC, 1993, pp:687-690 [Conf]
  16. Jason Agron, Wesley Peck, Erik Anderson, David L. Andrews, Ed Komp, Ron Sass, Fabrice Baijot, Jim Stevens
    Run-Time Services for Hybrid CPU/FPGA Systems on Chip. [Citation Graph (0, 0)][DBLP]
    RTSS, 2006, pp:3-12 [Conf]
  17. Ranjesh G. Jaganathan, Keith D. Underwood, Ron Sass
    A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC. [Citation Graph (0, 0)][DBLP]
    SC, 2003, pp:22- [Conf]
  18. Ron Sass, Matt W. Mutka
    Enabling unimodular transformations. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:753-762 [Conf]
  19. Keith D. Underwood, Walter B. Ligon III, Ron Sass
    Analysis of a prototype intelligent network interface. [Citation Graph (0, 0)][DBLP]
    Concurrency and Computation: Practice and Experience, 2003, v:15, n:7-8, pp:751-777 [Journal]
  20. Ron Sass, Brian Greskamp, Brian Leonard, Jeff Young, Srinivas Beeravolu
    Online architectures: A theoretical formulation and experimental prototype. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:319-333 [Journal]

  21. Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing. [Citation Graph (, )][DBLP]

  22. RBoot: Software Infrastructure for a Remote FPGA Laboratory. [Citation Graph (, )][DBLP]

  23. Quantifying Effective Memory Bandwidth of Platform FPGAs. [Citation Graph (, )][DBLP]

  24. FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAs. [Citation Graph (, )][DBLP]

  25. Reconfigurable Computing Cluster Project: Phase I Brief. [Citation Graph (, )][DBLP]

  26. AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks. [Citation Graph (, )][DBLP]

  27. RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function. [Citation Graph (, )][DBLP]

  28. A parallel/vectorized double-precision exponential core to accelerate computational science applications. [Citation Graph (, )][DBLP]

  29. Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores. [Citation Graph (, )][DBLP]

  30. Teaching FPGA system design via a remote laboratory facility. [Citation Graph (, )][DBLP]

  31. Hardware implementation of MPI_Barrier on an FPGA cluster. [Citation Graph (, )][DBLP]

  32. Scalability Studies of the BLASTn Scan and Ungapped Extension Functions. [Citation Graph (, )][DBLP]

  33. A Hardware Filesystem Implementation for High-Speed Secondary Storage. [Citation Graph (, )][DBLP]

  34. FPGA-based three-body molecular dynamics simulator. [Citation Graph (, )][DBLP]

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