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Publications of Author

1. Juan L. Aragón, Alexander V. Veidenbaum
   Energy-Effective Instruction Fetch Unit for Wide Issue Processors. [Citation Graph (0, 0)][DBLP]
   Asia-Pacific Computer Systems Architecture Conference, 2005, pp:15-27 [Conf]
   
2. Antonio Flores, Juan L. Aragón, Manuel E. Acacio
   Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. [Citation Graph (0, 0)][DBLP]
   AINA Workshops (1), 2007, pp:752-757 [Conf]
   
3. Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras
   Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2007, pp:113-122 [Conf]
   
4. Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu
   Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1374-1375 [Conf]
   
5. Juan L. Aragón, José González, José M. García, Antonio González
   Confidence Estimation for Branch Prediction Reversal. [Citation Graph (0, 0)][DBLP]
   HiPC, 2001, pp:214-223 [Conf]
   
6. Juan L. Aragón, José González, Antonio González
   Power-Aware Control Speculation through Selective Throttling. [Citation Graph (0, 0)][DBLP]
   HPCA, 2003, pp:103-112 [Conf]
   
7. Juan L. Aragón, José González, José M. García, Antonio González
   Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. [Citation Graph (0, 0)][DBLP]
   ICCD, 2001, pp:228-233 [Conf]
   
8. Juan L. Aragón, José González, Antonio González, James E. Smith
   Dual path instruction processing. [Citation Graph (0, 0)][DBLP]
   ICS, 2002, pp:220-229 [Conf]
   
9. Juan L. Aragón, José M. González, Antonio González
   Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:281-291 [Journal]
   
10. Juan M. Cebrian, Juan L. Aragón, José M. García
    Leakage Energy Reduction in Value Predictors through Static Decay. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
    
11. 
    MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance. [Citation Graph (, )][DBLP]
    
    
12. 
    REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs. [Citation Graph (, )][DBLP]
    
    
13. 
    Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. [Citation Graph (, )][DBLP]
    
    
14. 
    Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. [Citation Graph (, )][DBLP]
    
    
15. 
    Efficient microarchitecture policies for accurately adapting to power constraints. [Citation Graph (, )][DBLP]
    
    
16. 
    Extending SRT for parallel applications in tiled-CMP architectures. [Citation Graph (, )][DBLP]
    
    
17. 
    Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. [Citation Graph (, )][DBLP]