The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Thambipillai Srikanthan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wu Jigang, Thambipillai Srikanthan
    Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:440-448 [Conf]
  2. Wu Jigang, Thambipillai Srikanthan, Chengbin Yan
    Minimizing Power in Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:580-588 [Conf]
  3. Siew Kei Lam, Deng Yun, Thambipillai Srikanthan
    Morphable Structures for Reconfigurable Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:450-463 [Conf]
  4. H. Tian, Thambipillai Srikanthan, Vijayan K. Asari
    A Recursive Otsu-Iris Filter Technique for High-Speed Detection of Lumen Region from Endoscopic Images. [Citation Graph (0, 0)][DBLP]
    AIPR, 2001, pp:182-186 [Conf]
  5. Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya
    Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:373-379 [Conf]
  6. Bimal Gisutham, Thambipillai Srikanthan, K. Vijayan Asari
    A High Speed Flat CORDIC Based Neuron with Multi-Level Activation Function for Robust Pattern Recognition. [Citation Graph (0, 0)][DBLP]
    CAMP, 2000, pp:87-94 [Conf]
  7. Wu Jigang, Heiko Schröder, Thambipillai Srikanthan
    New Architecture and Algorithms for Degradable VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP]
    COCOON, 2002, pp:181-190 [Conf]
  8. Pramod K. Meher, Thambipillai Srikanthan, M. Mahesh Kumar, S. Arunkumar
    Low-Power Transform-Domain Coding by Separable Two-Dimensional Hartley-Like Transform. [Citation Graph (0, 0)][DBLP]
    Embedded Systems and Applications, 2003, pp:228-236 [Conf]
  9. Wu Jigang, Thambipillai Srikanthan, Chandni R. Patel
    A Low Power Algorithm for Reconfigurable VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP]
    Embedded Systems and Applications, 2003, pp:237-242 [Conf]
  10. Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke, Saurav Bhattacharyya
    Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design. [Citation Graph (0, 0)][DBLP]
    Embedded Systems and Applications, 2003, pp:210-215 [Conf]
  11. Siew Kei Lam, Mohammed Shoaib, Thambipillai Srikanthan
    Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:237-242 [Conf]
  12. Leipo Yan, Siew Kei Lam, Thambipillai Srikanthan, Wu Jigang
    Energy Efficient Cache Tuning with Performance Bound. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:97-100 [Conf]
  13. Rui Xiao, Chip-Hong Chang, Thambipillai Srikanthan
    On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:321-325 [Conf]
  14. Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya
    Dynamic Filter Cache for Low Power Instruction Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:607-610 [Conf]
  15. Thambipillai Srikanthan, Gurdeep S. Hura, Chia Cher Yong
    An Object Oriented GUI for Clustering Technique Based Network Simulations. [Citation Graph (0, 0)][DBLP]
    ESM, 1998, pp:92-96 [Conf]
  16. Wu Jigang, Thambipillai Srikanthan, Heiko Schröder
    Efficient Techniques and Hardware Analysis for Mesh-Connected Processors. [Citation Graph (0, 0)][DBLP]
    ICA3PP, 2005, pp:442-446 [Conf]
  17. Wu Jigang, Thambipillai Srikanthan
    On the Reconfiguration Algorithm for Fault-Tolerant VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science, 2003, pp:360-366 [Conf]
  18. Abhijit Ray, Wu Jigang, Thambipillai Srikanthan
    Knapsack Model and Algorithm for HW/SW Partitioning Problem. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science, 2004, pp:200-205 [Conf]
  19. Suchitra Sathyanarayana, Siew Kei Lam, Thambipillai Srikanthan
    High-throughput image rotation using sign-prediction based redundant cordic algorithm. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:2833-2836 [Conf]
  20. Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan
    New efficient residue-to-binary converters for 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup n+1/ - 1}. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:536-539 [Conf]
  21. Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan
    A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:656-659 [Conf]
  22. Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
    Design of a high speed reverse converter for a new 4-moduli set residue number system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:520-523 [Conf]
  23. Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
    A new design method to modulo 2/sup n/-1 squaring. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:664-667 [Conf]
  24. Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan
    A configurable dual moduli multi-operand modulo adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1630-1633 [Conf]
  25. Wu Jigang, Thambipillai Srikanthan
    Partial rerouting algorithm for reconfigurable VLSI arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:641-644 [Conf]
  26. Siew Kei Lam, Devendra K. Chaudhaiy, Thambipillai Srikanthan
    Low cost logarithmic techniques for high-precision computations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:125-128 [Conf]
  27. K. H. Quek, Siew Kei Lam, N. K. Agrawal, Thambipillai Srikanthan
    Architectural design and analysis toolbox to implement shortest path algorithms in hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:224-227 [Conf]
  28. H. Tian, Siew Kei Lam, Thambipillai Srikanthan
    Implementing Otsu's thresholding process using area-time efficient logarithmic approximation unit. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:21-24 [Conf]
  29. Yi Wang, Jussipekka Leiwo, Thambipillai Srikanthan
    Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1226-1229 [Conf]
  30. Wu Jigang, Thambipillai Srikanthan
    Fast reconfiguring mesh-connected VLSI arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:949-952 [Conf]
  31. Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
    Design of residue-to-binary converter for a new 5-moduli superset residue number system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:841-844 [Conf]
  32. C. S. Lim, Saman S. Abeysekera, T. Srikanthan, S. K. Amarasinghe
    Multiple sequence families with efficient hardware architecture for use in spread spectrum watermarking. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:761-764 [Conf]
  33. Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke
    Profile Directed Instruction Cache Tuning for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:277-282 [Conf]
  34. Yi Wang, Jussipekka Leiwo, Thambipillai Srikanthan, Yu Yu
    FPGA based DPA-resistant Unified Architecture for Signcryption. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:571-572 [Conf]
  35. Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya, Prasanna Venkatesh Kannan
    Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:44-47 [Conf]
  36. Abhijit Ray, Thambipillai Srikanthan, Wu Jigang
    Practical Techniques for Performance Estimation of Processors. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:308-311 [Conf]
  37. H. Tian, Thambipillai Srikanthan, Vijayan K. Asari
    A Hardware Efficient Technique for Rapid Lumen Segmentation from Endoscopic Images. [Citation Graph (0, 0)][DBLP]
    JCIS, 2002, pp:716-719 [Conf]
  38. Leipo Yan, Thambipillai Srikanthan, Niu Gang
    Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:182-188 [Conf]
  39. Gurdeep S. Hura, Sheeja Mohan, Thambipillai Srikanthan
    Load Sharing in Large Scale Distributed Systems: A Novel Approach. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:863-871 [Conf]
  40. Kugan Vivekanandarajah, Thambipillai Srikanthan
    Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:151-157 [Conf]
  41. H. Tian, Thambipillai Srikanthan, Vijayan K. Asari, Siew Kei Lam
    Study on the Effect of Object to Camera Distance on Polynomial Expansion Coefficients in Barrel Distortion Correction. [Citation Graph (0, 0)][DBLP]
    SSIAI, 2002, pp:255-259 [Conf]
  42. Wu Jigang, Thambipillai Srikanthan
    A Run-time Reconfiguration Algorithm for VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:567-572 [Conf]
  43. Dipnarayan Guha, Thambipillai Srikanthan
    Reconfigurable Frame Parser Design for Multi-Radio Support on Asynchronous Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
    ICCTA, 2007, pp:122-127 [Conf]
  44. Abhijit Ray, Wu Jigang, Thambipillai Srikanthan
    Knapsack Model and Algorithm for Hardware/Software Partitioning Problem. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  45. S. K. Leong, Thambipillai Srikanthan, Gurdeep S. Hura
    An Internet application for on-line banking. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1998, v:20, n:16, pp:1534-1540 [Journal]
  46. Siew Kei Lam, Thambipillai Srikanthan
    Dynamic multicast routing in VLSI. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2000, v:23, n:11, pp:1055-1063 [Journal]
  47. Thambipillai Srikanthan, Gurdeep S. Hura
    An efficient adaptive routing algorithm for a network management system. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1997, v:20, n:11, pp:988-998 [Journal]
  48. Wu Jigang, Thambipillai Srikanthan
    Low-complex dynamic programming algorithm for hardware/software partitioning. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2006, v:98, n:2, pp:41-46 [Journal]
  49. Wu Jigang, Thambipillai Srikanthan
    An efficient data structure for branch-and-bound algorithm. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 2004, v:167, n:1-4, pp:233-237 [Journal]
  50. Jigang Wu, Thambipillai Srikanthan
    An efficient algorithm for the collapsing knapsack problem. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 2006, v:176, n:12, pp:1739-1751 [Journal]
  51. Thambipillai Srikanthan, Bimal Gisuthan
    Optimizing Scaling Factor Computations in Flat Cordic. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:1, pp:17-34 [Journal]
  52. Wu Jigang, Thambipillai Srikanthan
    Power Efficient Sub-Array in Reconfigurable VLSI Meshes. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:5, pp:647-653 [Journal]
  53. Wu Jigang, Thambipillai Srikanthan
    An improved reconfiguration algorithm for degradable VLSI/WSI arrays. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:1-2, pp:23-31 [Journal]
  54. Siew Kei Lam, K. Sridharan, Thambipillai Srikanthan
    VLSI-efficient schemes for high-speed construction of tangent graph. [Citation Graph (0, 0)][DBLP]
    Robotics and Autonomous Systems, 2005, v:51, n:4, pp:248-260 [Journal]
  55. Wu Jigang, Thambipillai Srikanthan
    Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:3, pp:243-253 [Journal]
  56. Thambipillai Srikanthan, Siew Kei Lam, Mishra Suman
    Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:1, pp:69-72 [Journal]
  57. Gurdeep S. Hura, Thambipillai Srikanthan, Chia Cher Yong
    Network Simulation Environment (NSE): A Generic Framework for Network Graphs. [Citation Graph (0, 0)][DBLP]
    Telecommunication Systems, 2001, v:17, n:1-2, pp:213-231 [Journal]
  58. Wu Jigang, Thambipillai Srikanthan
    Algorithmic aspects of area-efficient hardware/software partitioning. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:38, n:3, pp:223-235 [Journal]
  59. Wu Jigang, Thambipillai Srikanthan, Heiko Schröder
    Efficient reconfigurable techniques for VLSI arrays with 6-port switches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:976-979 [Journal]
  60. Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
    Rapid generation of custom instructions using predefined dataflow structures. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:355-366 [Journal]
  61. Thambipillai Srikanthan, Bimal Gisuthan
    A novel technique for eliminating iterative based computation of polarity of micro-rotations in CORDIC based sine-cosine generators. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:26, n:5, pp:243-252 [Journal]
  62. Wu Jigang, Thambipillai Srikanthan, Guang Chen
    One-dimensional Search Algorithms for Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:149-158 [Conf]
  63. Wu Jigang, Thambipillai Srikanthan, Xiaodong Wang
    Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:10, pp:1387-1400 [Journal]

  64. Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection. [Citation Graph (, )][DBLP]


  65. Efficient Approximate Algorithm for Hardware/Software Partitioning. [Citation Graph (, )][DBLP]


  66. A Hybrid Branch-and-Bound Strategy for Hardware/Software Partitioning. [Citation Graph (, )][DBLP]


  67. Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors. [Citation Graph (, )][DBLP]


  68. Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors. [Citation Graph (, )][DBLP]


  69. Rapid estimation of instruction cache hit rates using loop profiling. [Citation Graph (, )][DBLP]


  70. Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms. [Citation Graph (, )][DBLP]


  71. Rapid design exploration framework for application-aware customization of soft core processors. [Citation Graph (, )][DBLP]


  72. Gradient angle histograms for efficient linear Hough transform. [Citation Graph (, )][DBLP]


  73. An Embedded Systems graduate education for Singapore. [Citation Graph (, )][DBLP]


  74. A Short Course on Implementing FPGA Based Digital Systems. [Citation Graph (, )][DBLP]


  75. Finding minimum interconnect sub-arrays in reconfigurable VLSI arrays. [Citation Graph (, )][DBLP]


  76. Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA. [Citation Graph (, )][DBLP]


  77. Instruction Cache Tuning for Embedded Multitasking Applications. [Citation Graph (, )][DBLP]


  78. Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms. [Citation Graph (, )][DBLP]


  79. A temperature-aware virtual submesh allocation scheme for noc-based manycore chips. [Citation Graph (, )][DBLP]


  80. Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations. [Citation Graph (, )][DBLP]


  81. Architecture-Aware Custom Instruction Generation for Reconfigurable Processors. [Citation Graph (, )][DBLP]


  82. Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems. [Citation Graph (, )][DBLP]


  83. New Reconfiguration Algorithm for Degradable VLSI Arrays. [Citation Graph (, )][DBLP]


  84. Efficient Algorithms for Hardware/Software Partitioning to Minimize Hardware Area. [Citation Graph (, )][DBLP]


  85. An Efficient Algorithm for DPA-resistent RSA. [Citation Graph (, )][DBLP]


  86. An efficient architecture for adaptive progressive thresholding. [Citation Graph (, )][DBLP]


  87. Incorporating area-time flexibility to a binary signed-digit adder. [Citation Graph (, )][DBLP]


  88. A MSB-biased self-organizing feature map for still color image compression. [Citation Graph (, )][DBLP]


  89. Fuzzy-ART based image compression for hardware implementation. [Citation Graph (, )][DBLP]


  90. Performance Estimation: IPC. [Citation Graph (, )][DBLP]


  91. Low Area-time Complexity Averaging Scheme for Thumbnail Generation. [Citation Graph (, )][DBLP]


  92. A Parallel Paths Communication Technique for Energy Efficient Wireless Sensor Networks. [Citation Graph (, )][DBLP]


Search in 0.183secs, Finished in 0.187secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002