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Neil W. Bergmann: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Neil W. Bergmann, Anwar S. Dawood
    Adaptive Interfacing with Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    ACSAC, 2001, pp:11-18 [Conf]
  2. David Brodrick, Anwar S. Dawood, Neil W. Bergmann, Melanie Wark
    Error Detection for Adaptive Computing Architectures in Spacecraft Applications. [Citation Graph (0, 0)][DBLP]
    ACSAC, 2001, pp:19-26 [Conf]
  3. Neil W. Bergmann, John A. Williams, Jie Han, Yi Chen
    A Process Model for Hardware Modules in Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:205-214 [Conf]
  4. David A. Kearney, Neil W. Bergmann
    Performance evaluation of asynchronous logic pipelines with data dependent processing delays. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:4-13 [Conf]
  5. David A. Kearney, Neil W. Bergmann
    Bundled Data Asynchronous Multipliers with Data Dependent Computation Times. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:186-197 [Conf]
  6. Neil W. Bergmann, J. Craig Mudge
    Automated Assistance for the Telemeeting Lifecycle. [Citation Graph (0, 0)][DBLP]
    CSCW, 1994, pp:373-384 [Conf]
  7. Reid B. Porter, Kevin McCabe, Neil W. Bergmann
    An Applications Approach to Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 1999, pp:170-174 [Conf]
  8. John W. Williams, Neil Bergmann
    Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:163-169 [Conf]
  9. Neil W. Bergmann, John A. Williams, Peter Waldeck
    Egret: A Flexible Platform for Real-Time Reconfigurable Systems on Chip. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:300-303 [Conf]
  10. Tien-Lung Lee, Neil W. Bergmann
    An Interface Methodology for Retargettable FPGA Peripherals. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:167-173 [Conf]
  11. Neil W. Bergmann, Yuk Ying Chung, Bernard K. Gunther
    Efficient implementation of the DCT on custom computers. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:244-245 [Conf]
  12. John A. Williams, Neil W. Bergmann, X. Xie
    FIFO Communication Models in Operating Systems for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:277-278 [Conf]
  13. John A. Williams, I. Syed, J. Wu, Neil W. Bergmann
    A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:351-352 [Conf]
  14. Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams
    VPN Acceleration Using Reconfigurable System-On-Chip Technology. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:281-282 [Conf]
  15. Gordon J. Brebner, Neil W. Bergmann
    Reconfigurable Computing in Remote and Harsh Environments. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:195-204 [Conf]
  16. Neil W. Bergmann, Peter R. Sutton
    A High-Performance Computing Module for a Low Earth Orbit Satellite Using Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:416-420 [Conf]
  17. Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann
    An FPGA Network Architecture for Accelerating 3DES - CBC. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:654-657 [Conf]
  18. Yi Lu, Neil W. Bergmann
    Dynamic Loading of Peripherals on Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:279-280 [Conf]
  19. Neil W. Bergmann, Yuk Ying Chung
    Video Compression on FPGA-Based Custom Computers. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 1997, pp:361-364 [Conf]
  20. Wilfried Osberger, Neil W. Bergmann, Anthony J. Maeder
    An Automatic Image Quality Assessment Technique Incorporating Higher Level Perceptual Factors. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1998, pp:414-418 [Conf]
  21. Sunil Shukla, Neil W. Bergmann, Jürgen Becker
    QUKU: A Two-Level Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:109-116 [Conf]
  22. Neil W. Bergmann, Peter Waldeck, John A. Williams
    A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:112-115 [Conf]
  23. Peter Waldeck, Neil W. Bergmann
    Dynamic Hardware-Software Partitioning on Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:102-105 [Conf]
  24. Reid B. Porter, Neil W. Bergmann
    Evolving FPGA Based Cellular Automata. [Citation Graph (0, 0)][DBLP]
    SEAL, 1998, pp:114-121 [Conf]
  25. Vera Y. Chung, Man To Wong, Neil W. Bergmann
    Fast search block-matching motion estimation algorithm using FPGA. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:913-921 [Conf]
  26. Anwar S. Dawood, Neil W. Bergmann, Zulfi Asdani, Boris Bravo
    Adaptive FIR filter design and implementation empowered by reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:1601-1612 [Conf]
  27. A. Cheung, Mohammed Bennamoun, Neil W. Bergmann
    An Arabic optical character recognition system using recognition-based segmentation. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 2001, v:34, n:2, pp:215-233 [Journal]
  28. Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams
    Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  29. Sunil Shukla, Neil W. Bergmann, Jürgen Becker
    QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
  30. Sunil Shukla, Neil W. Bergmann, Jürgen Becker
    QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:93-98 [Conf]

  31. QUKU: A Coarse Grained Paradigm for FPGAs. [Citation Graph (, )][DBLP]


  32. Automatic Self-Reconfiguration of System-on-Chip Peripherals. [Citation Graph (, )][DBLP]


  33. Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. [Citation Graph (, )][DBLP]


  34. System Level Design Methodology for Hybrid Multi-Processor SoC on FPGA. [Citation Graph (, )][DBLP]


  35. Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study. [Citation Graph (, )][DBLP]


  36. A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications. [Citation Graph (, )][DBLP]


  37. An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC. [Citation Graph (, )][DBLP]


  38. A Web Server Based Edge Detector Implementation in FPGA. [Citation Graph (, )][DBLP]


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