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Publications of Author

1. Mohan G. Kabadi, Ranjani Parthasarathi
   Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem. [Citation Graph (0, 0)][DBLP]
   Asia-Pacific Computer Systems Architecture Conference, 2003, pp:337-351 [Conf]
   
2. A. P. Shanthi, P. Muruganandam, Ranjani Parthasarathi
   Enhancing the Development Based Evolution of Digital Circuits. [Citation Graph (0, 0)][DBLP]
   Evolvable Hardware, 2004, pp:91-0 [Conf]
   
3. A. P. Shanthi, Ranjani Parthasarathi
   Exploring FPGA Structures for Evolving Fault Tolerant Hardware. [Citation Graph (0, 0)][DBLP]
   Evolvable Hardware, 2003, pp:184-191 [Conf]
   
4. A. P. Shanthi, L. Karthik Singaram, Ranjani Parthasarathi
   Evolution of Asynchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   Evolvable Hardware, 2005, pp:93-96 [Conf]
   
5. A. P. Shanthi, Balaji Vijayan, Manivel Rajendran, Senthilkumar Veluswami, Ranjani Parthasarathi
   JBits Based Fault Tolerant Framework for Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
   Engineering of Reconfigurable Systems and Algorithms, 2003, pp:111-117 [Conf]
   
6. Mohan G. Kabadi, Natarajan Kannan, Palanidaran Chidambaram, Suriya Narayanan, M. Subramanian, Ranjani Parthasarathi
   Dead-Block Elimination in Cache: A Mechanism to Reduce I-cache Power Consumption in High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
   HiPC, 2002, pp:79-88 [Conf]
   
7. R. Sharmila, M. V. Lakshmi Priya, Ranjani Parthasarathi
   An Active Framework for a WLAN Access Point Using Intel's IXP1200 Network Processor. [Citation Graph (0, 0)][DBLP]
   HiPC, 2004, pp:71-80 [Conf]
   
8. A. P. Shanthi, Ranjani Parthasarathi
   Genetic learning based fault tolerant models for digital systems. [Citation Graph (0, 0)][DBLP]
   Appl. Soft Comput., 2005, v:5, n:4, pp:357-371 [Journal]
   
9. V. Vetri Selvi, Shakir Sharfraz, Ranjani Parthasarathi
   Mobile Ad Hoc Grid Using Trace Based Mobility Model. [Citation Graph (0, 0)][DBLP]
   GPC, 2007, pp:274-285 [Conf]
   
10. 
    Evaluating the Network Processor Architecture for Application-Awareness. [Citation Graph (, )][DBLP]
    
    
11. 
    An ASM Model for an Autonomous Network-Infrastructure Grid. [Citation Graph (, )][DBLP]
    
    
12. 
    Trace Based Mobility Model for Ad Hoc Networks. [Citation Graph (, )][DBLP]
    
    
13. 
    Practical and scalable evolution of digital circuits. [Citation Graph (, )][DBLP]