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Woo-Chan Park: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Byung-Uck Kim, Woo-Chan Park, Sung-Bong Yang, Tack-Don Han
    A Cost-Effective Supersampling for Full Scene AntiAliasing. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:271-281 [Conf]
  2. Woo-Chan Park, Tack-Don Han, Sung-Bong Yang
    Order Independent Transparency for Image Composition Parallel Rendering Machines. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:449-460 [Conf]
  3. Woo-Chan Park, Tack-Don Han, Sung-Bong Yang
    A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:568-581 [Conf]
  4. Woo-Chan Park, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Kyung-Su Kim, Won-Jong Lee, Tack-Don Han, Sung-Bong Yang
    A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:160-175 [Conf]
  5. Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim
    In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:195-0 [Conf]
  6. Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang
    A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:173-0 [Conf]
  7. Won-Jong Lee, Hyung-Rae Kim, Woo-Chan Park, Jung-Woo Kim, Tack-Don Han, Sung-Bong Yang
    A New Bandwidth Reduction Method for Distributed Rendering Systems. [Citation Graph (0, 0)][DBLP]
    EurAsia-ICT, 2002, pp:387-394 [Conf]
  8. Won-Jong Lee, Woo-Chan Park, Jung-Woo Kim, Tack-Don Han, Sung-Bong Yang, Francis Neelamkavil
    A Bandwidth Reduction Scheme for 3D Texture-Based Volume Rendering on Commodity Graphics Hardware. [Citation Graph (0, 0)][DBLP]
    ICCSA (2), 2004, pp:741-750 [Conf]
  9. Moon-Hee Choi, Woo-Chan Park, Eun-Ji Lee, Shin-Dug Kim, Tack-Don Han
    A Pipelined Tiling-Traversal Unit for High Performance 3D Rendering Processor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1926-1931 [Conf]
  10. Eun-Ji Lee, Moon-Hee Choi, Woo-Chan Park, Shin-Dug Kim, Tack-Don Han
    Design of a Single Pass Rendering Pipeline for Occlusion Culling. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1932-1937 [Conf]
  11. Byung-Uck Kim, Kyoung-Wha Kim, Woo-Chan Park, Sung-Bong Yang, Tack-Don Han
    A Simple and Efficient Triangle Strip Filtering Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2005, v:21, n:6, pp:1277-1288 [Journal]
  12. Moon-Hee Choi, Woo-Chan Park, Francis Neelamkavil, Tack-Don Han, Shin-Dug Kim
    An Effective Visibility Culling Method Based on Cache Block. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:8, pp:1024-1032 [Journal]
  13. Jong-Chul Jeong, Woo-Chan Park, Woong Jeong, Tack-Don Han, Moon Key Lee
    A Cost-Effective Pipelined Divider with a Small Lookup Table. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:4, pp:483-489 [Journal]
  14. Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang
    An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1501-1508 [Journal]
  15. Kil-Whan Lee, Woo-Chan Park, Il-San Kim, Tack-Don Han
    A pixel cache architecture with selective placement scheme based on z-test result. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:1, pp:41-46 [Journal]
  16. Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Sung-Bong Yang, Moon Key Lee
    An effective out-of-order execution control scheme for an embedded floating point coprocessor. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:4, pp:171-180 [Journal]
  17. Seung-Gi Lee, Woo-Chan Park, Won-Jong Lee, Sung-Bong Yang, Tack-Don Han
    An Effective Bump Mapping Hardware Architecture Using Polar Coordinate System. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2007, v:23, n:2, pp:569-588 [Journal]
  18. Woo-Chan Park, Cheong-Ghil Kim, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Tack-Don Han
    A consistency-free memory architecture for sort-last parallel rendering processors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:272-284 [Journal]

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