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Kenji Kise: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kenji Kise, Hiroki Honda, Toshitsugu Yuba
    SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:122-136 [Conf]
  2. Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
    Effect of auto-tuning with user's knowledge for numerical software. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:12-25 [Conf]
  3. Ryo Takata, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
    DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  4. Takahiro Katagiri, Kenji Kise, Hiroaki Honda, Toshitsugu Yuba
    FIBER: A Generalized Framework for Auto-tuning Software. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:146-159 [Conf]
  5. Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba
    Evaluation of the Acknowledgment Reduction in a Software-DSM System. [Citation Graph (0, 0)][DBLP]
    PPAM, 2005, pp:17-25 [Conf]
  6. Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
    ABCLibScript: a directive to support specification of an auto-tuning facility for numerical software. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2006, v:32, n:1, pp:92-112 [Journal]
  7. Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
    ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2006, v:32, n:3, pp:231-250 [Journal]
  8. Sanya Tangpongprasit, Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
    A time-to-live based reservation algorithm on fully decentralized resource discovery in Grid computing. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2005, v:31, n:6, pp:529-543 [Journal]
  9. Satoshi Ohshima, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba
    Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2006, pp:305-318 [Conf]

  10. The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors. [Citation Graph (, )][DBLP]


  11. A Study of an Infrastructure for Research and Development of Many-Core Processors. [Citation Graph (, )][DBLP]


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