The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Chia-Lin Yang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung
    Cache Leakage Management for Multi-programming Workloads. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:736-749 [Conf]
  2. Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen
    Branch Behavior Characterization for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:523-530 [Conf]
  3. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen
    Temporal floorplanning using 3D-subTCG. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:725-730 [Conf]
  4. Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang
    Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:134-139 [Conf]
  5. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
    Placement of digital microfluidic biochips using the t-tree formulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:931-934 [Conf]
  6. Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
    Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:16-21 [Conf]
  7. Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, Chia-Lin Yang, Ai-Chun Pang, Tei-Wei Kuo
    Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2004, pp:101-108 [Conf]
  8. Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi
    Annotated Memory References: A Mechanism for Informed Cache Management. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1251-1254 [Conf]
  9. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
    Temporal floorplanning using the T-tree formulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:300-305 [Conf]
  10. Chia-Lin Yang, Alvin R. Lebeck
    Push vs. pull: data movement for linked data structures. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:176-186 [Conf]
  11. Chia-Lin Yang, Alvin R. Lebeck
    A Programmable Memory Hierarchy for Prefetching Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:160-174 [Conf]
  12. Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
    A power-aware SWDR cell for reducing cache write power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:14-17 [Conf]
  13. Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
    Joint exploration of architectural and physical design spaces with thermal consideration. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:123-126 [Conf]
  14. Chia-Lin Yang, Chien-Hao Lee
    HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:114-119 [Conf]
  15. Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang
    An energy-efficient virtual memory system with flash memory as the secondary storage. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:418-423 [Conf]
  16. Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King
    Hierarchical value cache encoding for off-chip data bus. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:143-146 [Conf]
  17. Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang
    A Space-Efficient Caching Mechanism for Flash-Memory Address Translation. [Citation Graph (0, 0)][DBLP]
    ISORC, 2006, pp:64-71 [Conf]
  18. Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
    Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:14-24 [Conf]
  19. Wan-Chun Ma, Chia-Lin Yang
    Using Intel Streaming SIMD Extensions for 3D Geometry Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Pacific Rim Conference on Multimedia, 2002, pp:1080-1087 [Conf]
  20. Tse-Tsung Shih, Chia-Lin Yang, Yi-Shin Tung
    Workload Characterization of the H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    PCM (2), 2004, pp:957-966 [Conf]
  21. Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen
    Reconfigurable Platform for Content Science Research. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:481-486 [Conf]
  22. Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang
    Profit-driven uniprocessor scheduling with energy and timing constraints. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:834-840 [Conf]
  23. Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su
    An architectural co-synthesis algorithm for energy-aware network-on-chip design. [Citation Graph (0, 0)][DBLP]
    SAC, 2007, pp:680-684 [Conf]
  24. Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee
    Tolerating memory latency through push prefetching for pointer-intensive applications. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:4, pp:445-475 [Journal]
  25. Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
    Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:9, pp:934-946 [Journal]
  26. Chia-Lin Yang, Hong-Wei Tseng, Chia-Chiang Ho, Ja-Ling Wu
    Software-Controlled Cache Architecture for Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:5, pp:634-644 [Journal]
  27. Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
    Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:827-836 [Journal]
  28. Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jien-Jia Chen
    Cache leakage control mechanism for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:248-256 [Conf]
  29. Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King
    Energy-efficient real-time task scheduling with task rejection. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1629-1634 [Conf]
  30. Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang
    Efficient obstacle-avoiding rectilinear steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:127-134 [Conf]
  31. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
    Temporal floorplanning using the three-dimensional transitive closure subGraph. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]

  32. A progressive-ILP based routing algorithm for cross-referencing biochips. [Citation Graph (, )][DBLP]


  33. PM-COSYN: PE and memory co-synthesis for MPSoCs. [Citation Graph (, )][DBLP]


  34. BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. [Citation Graph (, )][DBLP]


  35. Thermal modeling for 3D-ICs with integrated microchannel cooling. [Citation Graph (, )][DBLP]


  36. 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. [Citation Graph (, )][DBLP]


  37. Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  38. PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. [Citation Graph (, )][DBLP]


  39. Dynamic thermal management for networked embedded systems under harsh ambient temperature variation. [Citation Graph (, )][DBLP]


Search in 0.004secs, Finished in 0.005secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002