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C. T. Clarke :
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P. C. Kwan , C. T. Clarke FPGAs for Improved Energy Efficiency in Processor Based Systems. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:440-449 [Conf ] M. Bhardwaj , T. Srikanthan , C. T. Clarke A Reverse Converter for the 4-moduli Superset {2^n-1, 2^n, 2^n+1, 2^(n+1)+1}. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 1999, pp:168-175 [Conf ] M. Bhardwaj , T. Srikanthan , C. T. Clarke VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 1999, pp:176-0 [Conf ] X. H. Xu , C. T. Clarke , S. R. Jones High performance code compression architecture for the embedded ARM/THUMB processor. [Citation Graph (0, 0)][DBLP ] Conf. Computing Frontiers, 2004, pp:451-456 [Conf ] Elimination of sign precomputation in flat CORDIC. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.003secs