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Shih-Lien Lu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chunrong Lai, Shih-Lien Lu
    Efficient Victim Mechanism on Sector Cache Organization. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:16-29 [Conf]
  2. Chunrong Lai, Shih-Lien Lu, Yurong Chen, Trista Chen
    Improving branch prediction accuracy with parallel conservative correctors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:334-341 [Conf]
  3. Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir
    Ditto Processor. [Citation Graph (0, 0)][DBLP]
    DSN, 2002, pp:525-536 [Conf]
  4. Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu
    Design, implementation, and verification of active cache emulator (ACE). [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:63-72 [Conf]
  5. Shih-Lien L. Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh
    An FPGA-based Pentium in a complete desktop system. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:53-59 [Conf]
  6. Shih-Lien Lu, Konrad Lai
    Implementation of HW$im - A Real-Time Configurable Cache Simulator. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:638-647 [Conf]
  7. Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller
    Advances of the Counterflow Pipeline Microarchitecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:230-236 [Conf]
  8. Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu
    Non-Stalling CounterFlow Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:334-341 [Conf]
  9. Shih-Chang Lai, Shih-Lien Lu
    Hardware-based Pointer Data Prefetcher. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:290-298 [Conf]
  10. Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu
    Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:12-20 [Conf]
  11. Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai
    Bloom filtering cache misses for accurate data speculation and prefetching. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:189-198 [Conf]
  12. Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy
    Fine-Grained Redundancy in Adders. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:317-321 [Conf]
  13. Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai
    Dynamic addressing memory arrays with physical locality. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:161-170 [Conf]
  14. Tong Liu, Shih-Lien Lu
    Performance improvement with circuit-level speculation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:348-355 [Conf]
  15. Shih-Lien Lu
    Speeding Up Processing with Approximation Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:3, pp:67-73 [Journal]
  16. Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu
    Device and circuit simulation interface for an integrated VLSI design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:9, pp:998-1004 [Journal]
  17. John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
    RAMP: Research Accelerator for Multiple Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:2, pp:46-57 [Journal]
  18. Shih-Lien Lu
    Implementation of micropipelines in enable/disable CMOS differential logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:338-341 [Journal]
  19. Chih-Ming Chang, Shih-Lien Lu
    Design of a static MIMD data flow processor using micropipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:370-378 [Journal]
  20. R. Ramachandran, Shih-Lien Lu
    Efficient arithmetic using self-timing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:445-454 [Journal]

  21. Circuit techniques for dynamic variation tolerance. [Citation Graph (, )][DBLP]

  22. Automatic multithreaded pipeline synthesis from transactional datapath specifications. [Citation Graph (, )][DBLP]

  23. Automatic pipelining from transactional datapath specifications. [Citation Graph (, )][DBLP]

  24. An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. [Citation Graph (, )][DBLP]

  25. Novel FPGA based Haar classifier face detection algorithm acceleration. [Citation Graph (, )][DBLP]

  26. Resilient circuits - Enabling energy-efficient performance and reliability. [Citation Graph (, )][DBLP]

  27. Improving the reliability of on-chip data caches under process variations. [Citation Graph (, )][DBLP]

  28. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. [Citation Graph (, )][DBLP]

  29. Reducing cache power with low-cost, multi-bit error-correcting codes. [Citation Graph (, )][DBLP]

  30. Resilient microprocessor design for high performance & energy efficiency. [Citation Graph (, )][DBLP]

  31. Low power adaptive pipeline based on instruction isolation. [Citation Graph (, )][DBLP]

  32. Improving cache lifetime reliability at ultra-low voltages. [Citation Graph (, )][DBLP]

  33. Content Addressable Memory for Low-Power and High-Performance Applications. [Citation Graph (, )][DBLP]

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