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Byung-Soo Choi :
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Byung-Soo Choi , Jeong-A. Lee , Dong-Soo Har High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2004, pp:170-184 [Conf ] Chan-Ho Park , Byung-Soo Choi , Dong-Ik Lee , Ho-Yong Choi Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure. [Citation Graph (0, 0)][DBLP ] ARVLSI, 2001, pp:202-212 [Conf ] Byung-Soo Choi , Dong-Wook Lee , Dong-Ik Lee The Design of Delay Insensitive Asynchronous 16-bit Microprocessor. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1999, pp:33-36 [Conf ] Eun-Gu Jung , Byung-Soo Choi , Dong-Ik Lee High performance asynchronous bus for SoC. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:505-508 [Conf ] Byung-Soo Choi , Dong-Ik Lee Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus. [Citation Graph (0, 0)][DBLP ] PATMOS, 2003, pp:520-529 [Conf ] Byung-Soo Choi Cost effective mixed-type value predictor using distributed classification method. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2005, v:29, n:10, pp:451-462 [Journal ] An $\Theta(\sqrt{n})$-depth Quantum Adder on a 2D NTC Quantum Computer Architecture [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.002secs