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Shuming Chen :
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Ma Pengyong , Chen Shuming MID: a Novel Coherency Protocol in Chip Multiprocessor. [Citation Graph (0, 0)][DBLP ] CIT, 2006, pp:50- [Conf ] Zhentao Li , Shuming Chen , Zhaoliang Li , Conghua Lei The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2006, pp:401-408 [Conf ] Dong Wang , Xiao Hu , Shuming Chen , Yang Guo Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2006, pp:488-494 [Conf ] Xiangyuan Liu , Shuming Chen Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:91-94 [Conf ] Xiao Hu , Pengyong Ma , Shuming Chen , Yang Guo , Xing Fang TraceDo: An On-Chip Trace System for Real-Time Debug and Optimization in Multiprocessor SoC. [Citation Graph (0, 0)][DBLP ] ISPA, 2006, pp:806-817 [Conf ] Pengyong Ma , Xiao Hu , Shuming Chen , Yang Guo Pseudo Share Data Cache in Multiprocessor: PSDMP. [Citation Graph (0, 0)][DBLP ] ISPA Workshops, 2006, pp:47-56 [Conf ] Dong Wang , Xiaowen Chen , Shuming Chen , Xing Fang , Shuwei Sun FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2007, pp:80-89 [Conf ] Xing Fang , Dong Wang , Shuming Chen Exploiting Thread-Level Parallelism of Irregular LDPC Decoder with Simultaneous Multi-threading Technique. [Citation Graph (0, 0)][DBLP ] APPT, 2007, pp:650-657 [Conf ] Shuwei Sun , Dong Wang , Shuming Chen A Highly Efficient Parallel Algorithm for H.264 Encoder Based on Macro-Block Region Partition. [Citation Graph (0, 0)][DBLP ] HPCC, 2007, pp:577-585 [Conf ] Shuming Chen , Pengyong Ma FROCM: A Fair and Low-Overhead Method in SMT Processor. [Citation Graph (0, 0)][DBLP ] HPCC, 2007, pp:566-576 [Conf ] Xiao Hu , Pengyong Ma , Shuming Chen Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor. [Citation Graph (0, 0)][DBLP ] ICESS, 2007, pp:67-79 [Conf ] Shuming Chen , Xiangyuan Liu A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs. [Citation Graph (0, 0)][DBLP ] NOCS, 2007, pp:75-82 [Conf ] SPVA: A novel digital signal processor architecture for Software Defined Radio. [Citation Graph (, )][DBLP ] Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. [Citation Graph (, )][DBLP ] A DRAM Precharge Policy Based on Address Analysis. [Citation Graph (, )][DBLP ] Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform. [Citation Graph (, )][DBLP ] Efficient Bit-Rate Estimation for Mode Decision of H.264/AVC. [Citation Graph (, )][DBLP ] Combinational logic SER estimation with the presence of re-convergence. [Citation Graph (, )][DBLP ] An Efficient Parallel Algorithm for H.264/AVC Encoder. [Citation Graph (, )][DBLP ] An On-Line Control Flow Checking Method for VLIW Processor. [Citation Graph (, )][DBLP ] Applications of On-chip Trace on Debugging Embedded Processor. [Citation Graph (, )][DBLP ] Analysis of Glitch Reconvergence in Combinational Logic SER Estimation. [Citation Graph (, )][DBLP ] Fast and Accurate Estimate SET Voltage Pulses from Transient Currents Induced by Heavy Ion. [Citation Graph (, )][DBLP ] M2 SI: An Improved Coherency Protocol in CMP. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.004secs