The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Lars Bengtsson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anders Lindström, Michael Nordseth, Lars Bengtsson, Amos Omondi
    Arithmetic Circuits Combining Residue and Signed-Digit Representations. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:246-257 [Conf]
  2. Do Quang Minh, Lars Bengtsson, Per Larsson-Edefors
    DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 2003, pp:767-772 [Conf]
  3. Niklas Therning, Lars Bengtsson
    Jalapeno: secentralized grid computing using peer-to-peer technology. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:59-65 [Conf]
  4. Andreas Lindahl, Lars Bengtsson
    A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:42-47 [Conf]
  5. Stefan Lund, Lars Bengtsson
    Synchronizing a High-Speed SIMD Processor Array. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:376-381 [Conf]
  6. Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
    Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:557-563 [Conf]
  7. Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
    Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:185-191 [Conf]
  8. Lars Bengtsson
    A VLSI Array Architecture for Artificial Neural Networks. [Citation Graph (0, 0)][DBLP]
    Neural Networks and Computational Intelligence, 2003, pp:50-57 [Conf]
  9. Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson
    Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:869-878 [Conf]
  10. Lars Bengtsson
    Clock Speed Limitation and Timing in a Radar Signal Processing Architecture. [Citation Graph (0, 0)][DBLP]
    SIP, 1999, pp:372-377 [Conf]
  11. A. Persson, L. Bengtsson
    Reverse conversion architectures for signed-digit residue number systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  12. Selecting back off algorithm in active RFID CSMA/CA based medium-access protocols. [Citation Graph (, )][DBLP]


  13. Protocols for Active RFID - The Energy Consumption Aspect. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002