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Weiwu Hu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu
    Processor Directed Dynamic Page Policy. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:109-122 [Conf]
  2. Hou Rui, Fuxin Zhang, Weiwu Hu
    A Memory Bandwidth Effective Cache Store Miss Policy. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:750-760 [Conf]
  3. Gang Shi, Mingchang Hu, Hongda Yin, Weiwu Hu, Zhimin Tang
    A shared virtual memory network with fast remote direct memory access and message passing. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2004, pp:495- [Conf]
  4. Weiwu Hu, Gang Shi, Fuxin Zhang
    Communication with Threads in Software DSM. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2001, pp:149-154 [Conf]
  5. Weiwu Hu, Weisong Shi, Zhimin Tang
    Write Detection in Home-Based Software DSMs. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:909-913 [Conf]
  6. Weiwu Hu, Fuxin Zhang, Haiming Liu
    A New Home-Based Software DSM Protocol for SMP Clusters. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:1132-1142 [Conf]
  7. Hou Rui, Longbing Zhang, Weiwu Hu
    A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:506-516 [Conf]
  8. M. Rasit Eskicioglu, T. Anthony Marsland, Weiwu Hu, Weisong Shi
    Evaluation of the JIAJIA Software DSM System on High Performance Computer Architectures. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  9. Weiwu Hu, Weisong Shi, Zhimin Tang
    JIAJIA: A Software DSM System Based on a New Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1999, pp:463-472 [Conf]
  10. Weiwu Hu, Weisong Shi, Zhimin Tang
    Adaptive Write Detection in Home-based Software DSMs. [Citation Graph (0, 0)][DBLP]
    HPDC, 1999, pp:- [Conf]
  11. Weisong Shi, Weiwu Hu, Zhimin Tang, M. Rasit Eskicioglu
    Dynamic Task Migration in Home-based Software DSM Systems. [Citation Graph (0, 0)][DBLP]
    HPDC, 1999, pp:- [Conf]
  12. Weiwu Hu
    A Graph Model for Investigating Memory Consistency. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:516-523 [Conf]
  13. Weiwu Hu, Weisong Shi, Zhimin Tang
    Reducing System Overheads in Home-based Software DSMs. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:167-0 [Conf]
  14. Haiming Liu, Weiwu Hu
    A Comparison of Two Strategies of Dynamic Data Prefetching in Software DSM. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:62- [Conf]
  15. Ge Zhang, Zichu Qi, Weiwu Hu
    A novel design of leading zero anticipation circuit with parallel error detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:676-679 [Conf]
  16. Weiwu Hu, Peisu Xia
    Event Ordering Condition for Correct Executions in Shared-Memory Systems. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1996, pp:84-89 [Conf]
  17. Weiwu Hu, Weisong Shi, Zhimin Tang
    Optimizing Home-Based Software DSM Protocols. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2001, v:4, n:3, pp:235-242 [Journal]
  18. Weiwu Hu, Fuxin Zhang, Haiming Liu
    Dynamic Data Prefetching in Home-Based Software DSMs. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2001, v:16, n:3, pp:231-241 [Journal]
  19. Weiwu Hu, Fuxin Zhang, Zusong Li
    Microarchitecture of the Godson-2 Processor. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:243-249 [Journal]
  20. Ge Zhang, Weiwu Hu, Zichu Qi
    Parallel Error Detection for Leading Zero Anticipation. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:901-906 [Journal]
  21. Weisong Shi, Weiwu Hu, Zhimin Tang
    An Interaction of Coherence Protocols and Memory Consistency Models in DSM Systems. [Citation Graph (0, 0)][DBLP]
    Operating Systems Review, 1997, v:31, n:4, pp:41-54 [Journal]
  22. Hou Rui, Longbing Zhang, Weiwu Hu
    Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:3, pp:200-211 [Journal]
  23. Hongbo Zeng, Kun Huang, Ming Wu, Weiwu Hu
    Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:304-314 [Conf]
  24. Jun Wang, Ge Zhang, Weiwu Hu
    An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3712-3715 [Conf]

  25. A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. [Citation Graph (, )][DBLP]


  26. A High Speed CMOS Transmitter and Rail-to-Rail Receiver. [Citation Graph (, )][DBLP]


  27. A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only). [Citation Graph (, )][DBLP]


  28. Fast complete memory consistency verification. [Citation Graph (, )][DBLP]


  29. Microarchitecture and Performance Analysis of Godson-2 SMT Processor. [Citation Graph (, )][DBLP]


  30. An interconnect-aware power efficient cache coherence protocol for CMPs. [Citation Graph (, )][DBLP]


  31. LReplay: a pending period based deterministic replay scheme. [Citation Graph (, )][DBLP]


  32. A synchronized variable frequency clock scheme in chip multiprocessors. [Citation Graph (, )][DBLP]


  33. Optimizing power and throughput for m-out-of-n encoded asynchronous circuits. [Citation Graph (, )][DBLP]


  34. Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor. [Citation Graph (, )][DBLP]


  35. Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. [Citation Graph (, )][DBLP]


  36. Global Clock, Physical Time Order and Pending Period Analysis in Multiprocessor Systems [Citation Graph (, )][DBLP]


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