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Publications of Author

1. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue
   An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
   Asia-Pacific Computer Systems Architecture Conference, 2006, pp:219-230 [Conf]
   
2. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
   Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
   DSD, 2005, pp:372-378 [Conf]
   
3. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori
   GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
   ERSA, 2006, pp:227-230 [Conf]
   
4. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi
   Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
   EUC, 2006, pp:722-731 [Conf]
   
5. Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour
   A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. [Citation Graph (0, 0)][DBLP]
   FPT, 2005, pp:307-308 [Conf]
   
6. Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami
   Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
7. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
   An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2006, v:30, n:1, pp:52-62 [Journal]
   
8. Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi
   Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:325-330 [Conf]
   
9. Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani
   A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. [Citation Graph (0, 0)][DBLP]
   FPL, 2006, pp:1-4 [Conf]
   
10. Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami
    Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:249-260 [Conf]
    
11. 
    A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. [Citation Graph (, )][DBLP]
    
    
12. 
    Design space exploration for a coarse grain accelerator. [Citation Graph (, )][DBLP]
    
    
13. 
    Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. [Citation Graph (, )][DBLP]
    
    
14. 
    Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. [Citation Graph (, )][DBLP]
    
    
15. 
    An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. [Citation Graph (, )][DBLP]