A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. [Citation Graph (, )][DBLP]
Design space exploration for a coarse grain accelerator. [Citation Graph (, )][DBLP]
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. [Citation Graph (, )][DBLP]
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. [Citation Graph (, )][DBLP]
Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. [Citation Graph (, )][DBLP]
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. [Citation Graph (, )][DBLP]
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