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Morteza Saheb Zamani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue
    An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:219-230 [Conf]
  2. Morteza Saheb Zamani, Graham R. Hellestrand
    A neural network approach to the placement problem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
    Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:372-378 [Conf]
  4. Arash Hariri, Reza Rastegar, K. Navi, Morteza Saheb Zamani, Mohammad Reza Meybodi
    Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2005, pp:294-297 [Conf]
  5. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori
    GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:227-230 [Conf]
  6. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi
    Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
    EUC, 2006, pp:722-731 [Conf]
  7. Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi
    Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:311-314 [Conf]
  8. Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour
    A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:307-308 [Conf]
  9. Hamid Reza Kheirabadi, Morteza Saheb Zamani
    An efficient net ordering algorithm for buffer insertion. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:521-524 [Conf]
  10. Ali Jahanian, Morteza Saheb Zamani
    Improved timing closure by early buffer planning in floor-placement design flow. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:558-563 [Conf]
  11. Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami
    Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  12. Morteza Saheb Zamani, Graham R. Hellestrand
    A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:49-52 [Conf]
  13. Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian
    Prediction and reduction of routing congestion. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:72-77 [Conf]
  14. Ali Jahanian, Morteza Saheb Zamani
    Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:411-415 [Conf]
  15. Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi
    An Efficient Analytical Approach to Path-Based Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:219-224 [Conf]
  16. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
    On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:428-436 [Conf]
  17. Morteza Saheb Zamani, Graham R. Hellestrand
    A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. [Citation Graph (0, 0)][DBLP]
    IWANN, 1995, pp:1128-1134 [Conf]
  18. Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei
    A novel reconfigurable hardware architecture for IP address lookup. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:81-90 [Conf]
  19. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
    An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:1, pp:52-62 [Journal]
  20. Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani
    A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  21. Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami
    Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:249-260 [Conf]

  22. Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. [Citation Graph (, )][DBLP]


  23. A cycle-based synthesis algorithm for reversible logic. [Citation Graph (, )][DBLP]


  24. Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. [Citation Graph (, )][DBLP]


  25. Design space exploration for a coarse grain accelerator. [Citation Graph (, )][DBLP]


  26. Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. [Citation Graph (, )][DBLP]


  27. Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. [Citation Graph (, )][DBLP]


  28. Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. [Citation Graph (, )][DBLP]


  29. Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. [Citation Graph (, )][DBLP]


  30. A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. [Citation Graph (, )][DBLP]


  31. Performance and Timing Yield Enhancement using Highway-on-Chip Planning. [Citation Graph (, )][DBLP]


  32. An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. [Citation Graph (, )][DBLP]


  33. Improving Latency of Quantum Circuits by Gate Exchanging. [Citation Graph (, )][DBLP]


  34. Improved performance and yield with chip master planning design methodology. [Citation Graph (, )][DBLP]


  35. A novel synthesis algorithm for reversible circuits. [Citation Graph (, )][DBLP]


  36. Performance Improvement of Physical Retiming with Shortcut Insertion. [Citation Graph (, )][DBLP]


  37. FPGA-Based Circuit Model Emulation of Quantum Algorithms. [Citation Graph (, )][DBLP]


  38. Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. [Citation Graph (, )][DBLP]


  39. Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. [Citation Graph (, )][DBLP]


  40. An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. [Citation Graph (, )][DBLP]


  41. An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. [Citation Graph (, )][DBLP]


  42. A tileable switch module architecture for homogeneous 3D FPGAs. [Citation Graph (, )][DBLP]


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