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Kazuaki Murakami: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue
    An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:219-230 [Conf]
  2. Takanori Okuma, Koji Hashimoto, Kazuaki Murakami
    Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:37-38 [Conf]
  3. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori
    GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:227-230 [Conf]
  4. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi
    Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
    EUC, 2006, pp:722-731 [Conf]
  5. Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami
    The effect of temperature on cache size tuning for low energy embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:453-456 [Conf]
  6. Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki Murakami
    Collective Communication Costs Analysis over Gigabit Ethernet and InfiniBand. [Citation Graph (0, 0)][DBLP]
    HiPC, 2006, pp:547-559 [Conf]
  7. Koji Inoue, Koji Kai, Kazuaki Murakami
    Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:218-222 [Conf]
  8. Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
    A Low Energy Set-Associative I-Cache with Extended BTB. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:187-0 [Conf]
  9. Takashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura
    A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:308-317 [Conf]
  10. Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita
    Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:272-281 [Conf]
  11. Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
    The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:351-360 [Conf]
  12. Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
    The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:995-1000 [Conf]
  13. Koji Inoue, Koji Kai, Kazuaki Murakami
    Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:169-178 [Conf]
  14. Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami
    Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  15. Kazuaki Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita
    SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:78-85 [Conf]
  16. Koji Inoue, Tohru Ishihara, Kazuaki Murakami
    Way-predicting set-associative cache for high performance and low energy consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:273-275 [Conf]
  17. Koji Inoue, Vasily G. Moshnyaga, Keikichi Murakami
    A history-based I-cache for low-energy multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:148-153 [Conf]
  18. Taku Ohsawa, Koji Kai, Kazuaki Murakami
    Optimizing the DRAM refresh count for merged DRAM/logic LSIs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:82-87 [Conf]
  19. Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga
    Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:179-186 [Conf]
  20. Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
    Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:18-32 [Conf]
  21. Hamid Noori, Kazuaki Murakami
    Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications. [Citation Graph (0, 0)][DBLP]
    SAC, 2006, pp:937-938 [Conf]
  22. Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki Murakami
    REDEFIS: a system with a redefinable instruction set processor. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:14-19 [Conf]
  23. Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi
    Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:325-330 [Conf]
  24. Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
    Task scheduling for reliable cache architectures of multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1490-1495 [Conf]
  25. Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani
    A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  26. Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami
    Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:249-260 [Conf]
  27. Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi. Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura
    A character size optimization technique for throughput enhancement of character projection lithography. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Takesi Soga, Kouji Kurihara, Takeshi Nanri, Motoyoshi Kurokawa, Kazuaki Murakami
    Dynamic Optimization of Load Balance in MPI Broadcast. [Citation Graph (0, 0)][DBLP]
    PVM/MPI, 2007, pp:387-388 [Conf]

  29. Empirical Performance Models for Java Workloads. [Citation Graph (, )][DBLP]


  30. A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. [Citation Graph (, )][DBLP]


  31. Design space exploration for a coarse grain accelerator. [Citation Graph (, )][DBLP]


  32. The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. [Citation Graph (, )][DBLP]


  33. Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. [Citation Graph (, )][DBLP]


  34. Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. [Citation Graph (, )][DBLP]


  35. Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. [Citation Graph (, )][DBLP]


  36. Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms. [Citation Graph (, )][DBLP]


  37. Performance prediction of large-scale parallell system and application using macro-level simulation. [Citation Graph (, )][DBLP]


  38. Circuit Area-latency Optimization Technique for High-precision Elementary Functions. [Citation Graph (, )][DBLP]


  39. Reducing power consumption of instruction ROMs by exploiting instruction frequency. [Citation Graph (, )][DBLP]


  40. A Dynamic Solution for Efficient MPI Collective Communications. [Citation Graph (, )][DBLP]


  41. Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units. [Citation Graph (, )][DBLP]


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