The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Mehdi Sedighi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue
    An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:219-230 [Conf]
  2. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
    Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:372-378 [Conf]
  3. Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari
    Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:227-230 [Conf]
  4. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori
    GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:227-230 [Conf]
  5. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi
    Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
    EUC, 2006, pp:722-731 [Conf]
  6. Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:269- [Conf]
  7. Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:296-301 [Conf]
  8. Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami
    Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  9. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
    On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:428-436 [Conf]
  10. Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:63-69 [Conf]
  11. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
    An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:1, pp:52-62 [Journal]

  12. A cycle-based synthesis algorithm for reversible logic. [Citation Graph (, )][DBLP]


  13. Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. [Citation Graph (, )][DBLP]


  14. Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. [Citation Graph (, )][DBLP]


  15. Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. [Citation Graph (, )][DBLP]


  16. A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. [Citation Graph (, )][DBLP]


  17. Improving Latency of Quantum Circuits by Gate Exchanging. [Citation Graph (, )][DBLP]


  18. A novel synthesis algorithm for reversible circuits. [Citation Graph (, )][DBLP]


  19. FPGA-Based Circuit Model Emulation of Quantum Algorithms. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002