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Publications of Author

1. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue
   An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
   Asia-Pacific Computer Systems Architecture Conference, 2006, pp:219-230 [Conf]
   
2. Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga
   Reducing Access Count to Register-Files through Operand Reuse. [Citation Graph (0, 0)][DBLP]
   Asia-Pacific Computer Systems Architecture Conference, 2003, pp:112-121 [Conf]
   
3. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi
   Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
   EUC, 2006, pp:722-731 [Conf]
   
4. Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami
   The effect of temperature on cache size tuning for low energy embedded systems. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:453-456 [Conf]
   
5. Koji Inoue, Koji Kai, Kazuaki Murakami
   Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. [Citation Graph (0, 0)][DBLP]
   HPCA, 1999, pp:218-222 [Conf]
   
6. Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
   A Low Energy Set-Associative I-Cache with Extended BTB. [Citation Graph (0, 0)][DBLP]
   ICCD, 2002, pp:187-0 [Conf]
   
7. Koji Inoue, Koji Kai, Kazuaki Murakami
   Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. [Citation Graph (0, 0)][DBLP]
   Intelligent Memory Systems, 2000, pp:169-178 [Conf]
   
8. Koji Inoue, Tohru Ishihara, Kazuaki Murakami
   Way-predicting set-associative cache for high performance and low energy consumption. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1999, pp:273-275 [Conf]
   
9. Koji Inoue, Vasily G. Moshnyaga, Keikichi Murakami
   A history-based I-cache for low-energy multimedia applications. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2002, pp:148-153 [Conf]
   
10. Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa
    Reducing energy consumption of video memory by bit-width compression. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:142-147 [Conf]
    
11. Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
    Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:18-32 [Conf]
    
12. Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga
    Register File Energy Reduction by Operand Data Reuse. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:278-288 [Conf]
    
13. Shigeharu Matsusaka, Koji Inoue
    A Cost Effective Spacial Redundancy with Data-Path Partitioning. [Citation Graph (0, 0)][DBLP]
    ICITA (2), 2005, pp:51-56 [Conf]
    
14. Koji Inoue
    Energy-security tradeoff in a secure cache architecture against buffer overflow attacks. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:81-89 [Journal]
    
15. Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi
    Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:325-330 [Conf]
    
16. Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani
    A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
    
17. Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami
    Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:249-260 [Conf]
    
18. Toshiya Takami, Jun Maki, Jun-ichi Ooba, Yuichi Inadomi, Hiroaki Honda, Ryutaro Susukita, Koji Inoue, Taizo Kobayashi, Rie Nogita, Mutsumi Aoyagi
    Multi-physics Extension of OpenFMO Framework [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
19. 
    A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. [Citation Graph (, )][DBLP]
    
    
20. 
    Design space exploration for a coarse grain accelerator. [Citation Graph (, )][DBLP]
    
    
21. 
    The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. [Citation Graph (, )][DBLP]
    
    
22. 
    Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. [Citation Graph (, )][DBLP]
    
    
23. 
    Improved Policies for Drowsy Caches in Embedded Processors. [Citation Graph (, )][DBLP]
    
    
24. 
    Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. [Citation Graph (, )][DBLP]
    
    
25. 
    Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. [Citation Graph (, )][DBLP]
    
    
26. 
    Performance prediction of large-scale parallell system and application using macro-level simulation. [Citation Graph (, )][DBLP]
    
    
27. 
    Multiplier energy reduction through bypassing of partial products. [Citation Graph (, )][DBLP]
    
    
28. 
    Reducing power consumption of instruction ROMs by exploiting instruction frequency. [Citation Graph (, )][DBLP]