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Publications of Author

1. Mehdi Modarressi, Maziar Goudarzi, Shaahin Hessabi
   Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance. [Citation Graph (0, 0)][DBLP]
   Asia-Pacific Computer Systems Architecture Conference, 2005, pp:761-774 [Conf]
   
2. Alireza Poshtkuhi, Ali Haj Abutalebi, Leila Mahmoudi Ayough, Shaahin Hessabi
   DotGrid: A .NET-based Infrastructure for Global Grid Computing. [Citation Graph (0, 0)][DBLP]
   CCGRID, 2006, pp:61- [Conf]
   
3. Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali
   A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. [Citation Graph (0, 0)][DBLP]
   ESA/VLSI, 2004, pp:582-588 [Conf]
   
4. Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft
   Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1380-1381 [Conf]
   
5. Mehdi Modarressi, Shaahin Hessabi, Maziar Goudarzi
   A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling. [Citation Graph (0, 0)][DBLP]
   DELTA, 2006, pp:249-254 [Conf]
   
6. Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi
   Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:329-334 [Conf]
   
7. Mahdi Fazeli, Reza Farivar, Shaahin Hessabi, Seyed Ghassem Miremadi
   A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
   LADC, 2005, pp:143-153 [Conf]
   
8. Maziar Goudarzi, Shaahin Hessabi
   The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2005, pp:394-403 [Conf]
   
9. Khadijeh Khamei, Abdolreza Nabavi, Shaahin Hessabi, Seyed Ahmad Mohseni Barandagh
   Design of Variable Fractional Delay Fir Filters with Csd Coefficients Using Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:6, pp:1145-1156 [Journal]
   
10. Nikzad Babaii Rizvandi, Abdolreza Nabavi, Shaahin Hessabi
    An Accurate Fir Approximation of Ideal Fractional Delay Filter with Complex Coefficients in Hilbert Space. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:3, pp:497-506 [Journal]
    
11. Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft
    Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2004, v:10, n:9, pp:1123-1155 [Journal]
    
12. Shaahin Hessabi, Mehdi Modarressi, Maziar Goudarzi, Hani JavanHemmat
    A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:7-13 [Conf]
    
13. Mehdi Modarressi, Shaahin Hessabi, Maziar Goudarzi
    A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:959-962 [Conf]
    
14. Hani JavanHemmat, Maziar Goudarzi, Shaahin Hessabi
    On the Hardware-Software Partitioning: The Classic General Model (CGM). [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:1922-1925 [Conf]
    
15. Shaahin Hessabi, M. Y. Osman, Mohamed I. Elmasry
    Differential BiCMOS logic circuits: fault characterization and design-for-testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:437-445 [Journal]
    
16. Amir Masoud Gharehbaghi, Benyamin Hamdin Yaran, Shaahin Hessabi, Maziar Goudarzi
    An assertion-based verification methodology for system-level design. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:4, pp:269-284 [Journal]
    
17. 
    An Adaptive Approach to Manage the Number of Virtual Channels. [Citation Graph (, )][DBLP]
    
    
18. 
    PERMAP: A performance-aware mapping for application-specific SoCs. [Citation Graph (, )][DBLP]
    
    
19. 
    Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs. [Citation Graph (, )][DBLP]
    
    
20. 
    An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models. [Citation Graph (, )][DBLP]
    
    
21. 
    An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits. [Citation Graph (, )][DBLP]
    
    
22. 
    Low Power Encoding in NoCs Based on Coupling Transition Avoidance. [Citation Graph (, )][DBLP]
    
    
23. 
    Caspian: A Tunable Performance Model for Multi-core Systems. [Citation Graph (, )][DBLP]
    
    
24. 
    A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips. [Citation Graph (, )][DBLP]
    
    
25. 
    A Markovian Performance Model for Networks-on-Chip. [Citation Graph (, )][DBLP]
    
    
26. 
    Hierarchical on-Chip Routing of Optical Packets in Large Scale MPSoCs. [Citation Graph (, )][DBLP]
    
    
27. 
    High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs. [Citation Graph (, )][DBLP]
    
    
28. 
    Contention-free on-chip routing of optical packets. [Citation Graph (, )][DBLP]
    
    
29. 
    Object-Oriented ASIP Design and Synthesis. [Citation Graph (, )][DBLP]