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Seyed Ghassem Miremadi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. N. Amini, Mahdi Fazeli, Seyed Ghassem Miremadi, M. T. Manzuri
    Distance-Based Segmentation: An Energy-Efficient Clustering Hierarchy for Wireless Microsensor Networks. [Citation Graph (0, 0)][DBLP]
    CNSR, 2007, pp:18-25 [Conf]
  2. Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali
    A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:582-588 [Conf]
  3. Ali Reza Ejlali, Seyed Ghassem Miremadi
    Switch-level emulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:644-649 [Conf]
  4. Ahmad Patooghy, Seyed Ghassem Miremadi, A. Javadtalab, Mahdi Fazeli, N. Farazmand
    A Solution to Single Point of Failure Using Voter Replication and Disagreement Detection. [Citation Graph (0, 0)][DBLP]
    DASC, 2006, pp:171-176 [Conf]
  5. Mahdi Fazeli, Reza Farivar, Seyed Ghassem Miremadi
    A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:266-274 [Conf]
  6. Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
    Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:485-492 [Conf]
  7. Yasser Sedaghat, Seyed Ghassem Miremadi, Mahdi Fazeli
    A Software-Based Error Detection Technique Using Encoded Signatures. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:389-400 [Conf]
  8. Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
    A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. [Citation Graph (0, 0)][DBLP]
    DSN, 2003, pp:479-0 [Conf]
  9. Hamid R. Zarandi, Seyed Ghassem Miremadi
    Hierarchical Multiple Associative Mapping in Cache Memories. [Citation Graph (0, 0)][DBLP]
    ECBS, 2005, pp:95-101 [Conf]
  10. Seyed Ghassem Miremadi, Ali Reza Ejlali
    Switch Level Fault Emulation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:849-858 [Conf]
  11. Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali
    Fast Prototyping with Co-operation of Simulation and Emulation. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:15-25 [Conf]
  12. Mostafa Shaad Zolpirani, Mohammad-Mahdi Bidmeshki, Seyed Ghassem Miremadi
    Improving Network's Performability Using Parallel Processing. [Citation Graph (0, 0)][DBLP]
    ICN, 2007, pp:40- [Conf]
  13. Reza Farivar, Mahdi Fazeli, Seyed Ghassem Miremadi
    Directed Flooding: A Fault-Tolerant Routing Protocol for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ICW/ICHSN/ICMCS/SENET, 2005, pp:395-399 [Conf]
  14. Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour
    Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:239-246 [Conf]
  15. Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad
    Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:101-108 [Conf]
  16. Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger
    Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:281-286 [Conf]
  17. Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
    Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. [Citation Graph (0, 0)][DBLP]
    ISPDC, 2003, pp:281-0 [Conf]
  18. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:380-385 [Conf]
  19. Mahdi Fazeli, Reza Farivar, Shaahin Hessabi, Seyed Ghassem Miremadi
    A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    LADC, 2005, pp:143-153 [Conf]
  20. Hamid R. Zarandi, Seyed Ghassem Miremadi
    Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme. [Citation Graph (0, 0)][DBLP]
    LADC, 2005, pp:121-130 [Conf]
  21. Mohammad Hadi Valavi, Seyed Ghassem Miremadi
    Reliability Evaluation Using Fault Trees Based on Monte Carlo Simulation. [Citation Graph (0, 0)][DBLP]
    MSV/AMCS, 2004, pp:477-480 [Conf]
  22. Hakem Beitollahi, Seyed Ghassem Miremadi
    Performance Evaluation of Fault-Tolerant Scheduling Algorithms in Real-Time Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2005, pp:479-484 [Conf]
  23. Somayeh Timarchi, Seyed Ghassem Miremadi, Ali Reza Ejlali
    Evaluation of Some Exponential Random Number Generators Implemented by FPGA. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2005, pp:578-583 [Conf]
  24. Hassan Salmani, Seyed Ghassem Miremadi
    Assessment of Message Missing Failures in CAN-based Systems. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2005, pp:387-392 [Conf]
  25. Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali
    Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    PRDC, 2004, pp:327-332 [Conf]
  26. Amir Rajabzadeh, Mirzad Mohandespour, Seyed Ghassem Miremadi
    Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features. [Citation Graph (0, 0)][DBLP]
    PRDC, 2004, pp:49-54 [Conf]
  27. Amir Rajabzadeh, Seyed Ghassem Miremadi
    A Hardware Approach to Concurrent Error Detection Capability Enhancement in COTS Processors. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:83-90 [Conf]
  28. Hassan Salmani, Seyed Ghassem Miremadi
    Contribution of Controller Area Networks Controllers to Masquerade Failures. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:310-316 [Conf]
  29. Hamid R. Zarandi, Seyed Ghassem Miremadi
    A Highly Fault Detectable Cache Architecture for Dependable Computing. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2004, pp:45-59 [Conf]
  30. Mahdi Kefayati, Hamid R. Rabiee, Seyed Ghassem Miremadi, Ahmad Khonsari
    Misbehavior resilient multi-path data transmission in mobile ad-hoc networks. [Citation Graph (0, 0)][DBLP]
    SASN, 2006, pp:91-100 [Conf]
  31. Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi
    Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:323-335 [Journal]
  32. Alireza Ejlali, Seyed Ghassem Miremadi
    FPGA-based fault injection into switch-level models. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:317-327 [Journal]
  33. Alireza Ejlali, Seyed Ghassem Miremadi
    FPGA-based Monte Carlo simulation for fault tree analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:6, pp:1017-1028 [Journal]
  34. Amir Rajabzadeh, Seyed Ghassem Miremadi
    CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:5-6, pp:959-972 [Journal]
  35. Hamid R. Zarandi, Seyed Ghassem Miremadi
    A fault-tolerant cache architecture based on binary set partitioning. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:1, pp:86-99 [Journal]
  36. Amir Rajabzadeh, Seyed Ghassem Miremadi
    Transient detection in COTS processors using software approach. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:1, pp:124-133 [Journal]
  37. Hamid R. Zarandi, Seyed Ghassem Miremadi
    Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:2-3, pp:461-470 [Journal]
  38. Mostafa Shaad Zolpirani, Mohammad-Mahdi Bidmeshki, Seyed Ghassem Miremadi
    The Effect of Routing-Update Time on Network's Performability. [Citation Graph (0, 0)][DBLP]
    AICCSA, 2007, pp:655-658 [Conf]
  39. Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi
    Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1647-1652 [Conf]
  40. Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali
    Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:276-285 [Conf]
  41. Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
    Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  42. Hakem Beitollahi, Seyed Ghassem Miremadi, Geert Deconinck
    Fault-Tolerant Earliest-Deadline-First Scheduling Algorithm. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  43. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3675-3678 [Conf]
  44. Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
    CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3696-3699 [Conf]
  45. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:141-144 [Conf]

  46. FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption. [Citation Graph (, )][DBLP]


  47. Analyzing fault effects in the 32-bit OpenRISC 1200 microprocessor. [Citation Graph (, )][DBLP]


  48. Fault Effects in FlexRay-Based Networks with Hybrid Topology. [Citation Graph (, )][DBLP]


  49. A Micro-FT-UART for Safety-Critical SoC-Based Applications. [Citation Graph (, )][DBLP]


  50. Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies. [Citation Graph (, )][DBLP]


  51. A High Speed and Low Cost Error Correction Technique for the Carry Select Adder. [Citation Graph (, )][DBLP]


  52. A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET. [Citation Graph (, )][DBLP]


  53. An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors. [Citation Graph (, )][DBLP]


  54. An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors. [Citation Graph (, )][DBLP]


  55. Control-Flow Checking Using Branch Instructions. [Citation Graph (, )][DBLP]


  56. A Low Power Error Detection Technique for Floating-Point Units in Embedded Applications. [Citation Graph (, )][DBLP]


  57. A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors. [Citation Graph (, )][DBLP]


  58. A low-cost fault-tolerant technique for Carry Look-Ahead adder. [Citation Graph (, )][DBLP]


  59. Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off. [Citation Graph (, )][DBLP]


  60. XYX: A Power & Performance Efficient Fault-Tolerant Routing Algorithm for Network on Chip. [Citation Graph (, )][DBLP]


  61. A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips. [Citation Graph (, )][DBLP]


  62. Assessment of Message Missing Failures in FlexRay-Based Networks. [Citation Graph (, )][DBLP]


  63. Investigation and Reduction of Fault Sensitivity in the FlexRay Communication Controller Registers. [Citation Graph (, )][DBLP]


  64. A Power Efficient Approach to Fault-Tolerant Register File Design. [Citation Graph (, )][DBLP]


  65. Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers. [Citation Graph (, )][DBLP]


  66. FPGA-Based Fault Injection into Synthesizable Verilog HDL Models. [Citation Graph (, )][DBLP]


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