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Partha S. Roop: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Partha S. Roop, Arcot Sowmya, S. Ramesh
    Automated Component Adaptation by Forced Simulation. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:74-81 [Conf]
  2. Partha S. Roop, Arcot Sowmya, S. Ramesh
    A formal approach to component based development of synchronous programs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:421-424 [Conf]
  3. Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari
    REMIC: design of a reactive embedded microprocessor core. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:977-981 [Conf]
  4. Zoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic
    HiDRA: A New Architecture for Heterogeneous Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:164-170 [Conf]
  5. Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Dayaratne
    Towards direct execution of esterel programs on reactive processors. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:240-248 [Conf]
  6. Zoran A. Salcic, Partha S. Roop
    Customizing Processor Cores to Support Reactivity. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:194-202 [Conf]
  7. Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli
    REFLIX: A Processor Core for Reactive Embedded Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:945-945 [Conf]
  8. Partha S. Roop, Arcot Sowmya, S. Ramesh
    k-time Forced Simulation: A Formal Verification Technique for IP Reuse. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:50-55 [Conf]
  9. Robi Malik, Partha S. Roop
    Adaptive Techniques for Specification Matching in Embedded Systems: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    IFM, 2005, pp:33-52 [Conf]
  10. Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid
    A Scheduler Support Unit for Reactive Microprocessors. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:368-372 [Conf]
  11. Raj S. Mitra, Partha S. Roop, Anupam Basu
    Implementation of design functions by available devices: a new algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:30-35 [Conf]
  12. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:461-464 [Conf]
  13. Partha S. Roop, Arcot Sowmya
    CFSMcharts: A New Language for Microprocessor Based system Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:342-346 [Conf]
  14. Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli
    A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:189-194 [Conf]
  15. Partha S. Roop, Arcot Sowmya, S. Ramesh
    Automatic Component Matching Using Forced Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:64-69 [Conf]
  16. Rick Mugridge, Bruce MacDonald, Partha S. Roop
    A Customer Test Generator for Web-Based Systems. [Citation Graph (0, 0)][DBLP]
    XP, 2003, pp:189-197 [Conf]
  17. Rick Mugridge, Bruce MacDonald, Partha S. Roop, Ewan D. Tempero
    Five Challenges in Teaching XP. [Citation Graph (0, 0)][DBLP]
    XP, 2003, pp:406-409 [Conf]
  18. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    Modeling Embedded Systems: From SystemC and Esterel to DFCharts. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:348-358 [Journal]
  19. Roopak Sinha, Partha S. Roop, Bakhadyr Khoussainov
    Adaptive Verification using Forced Simulation. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:141, n:3, pp:171-197 [Journal]
  20. Samik Basu, Partha S. Roop, Roopak Sinha
    Local Module Checking for CTL Specifications. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:176, n:2, pp:125-141 [Journal]
  21. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    A New Model for Heterogeneous Embedded Systems - What Esterel and SyncCharts Need to Become a Suitable Specification Platform. [Citation Graph (0, 0)][DBLP]
    International Journal of Software Engineering and Knowledge Engineering, 2005, v:15, n:2, pp:405-410 [Journal]
  22. Hai-Feng Guo, Miao Liu, Partha S. Roop, C. R. Ramakrishnan, I. V. Ramakrishnan
    Precise specification matching for adaptive reuse in embedded systems. [Citation Graph (0, 0)][DBLP]
    J. Applied Logic, 2007, v:5, n:2, pp:333-355 [Journal]
  23. Partha S. Roop, Arcot Sowmya, S. Ramesh
    Forced simulation: A technique for automating component reuse in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:602-628 [Journal]
  24. Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari
    HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:2, pp:72-85 [Journal]
  25. Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli
    REFLIX: a processor core with native support for control-dominated embedded applications. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:1, pp:13-25 [Journal]
  26. Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic
    The SystemJ approach to system-level design. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:149-158 [Conf]
  27. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    McCharts and Multiclock FSMs for modeling large scale systems. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:3-12 [Conf]
  28. Raj S. Mitra, Partha S. Roop, Anupam Basu
    A new algorithm for implementation of design functions by available devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:170-180 [Journal]

  29. Specification Enforcing Refinement for Convertibility Verification. [Citation Graph (, )][DBLP]


  30. Tight WCRT analysis of synchronous C programs. [Citation Graph (, )][DBLP]


  31. Multi-clock Soc design using protocol conversion. [Citation Graph (, )][DBLP]


  32. Deterministic, predictable and light-weight multithreading using PRET-C. [Citation Graph (, )][DBLP]


  33. Hidden time model for specification and verification of embedded systems. [Citation Graph (, )][DBLP]


  34. A Module Checking Based Converter Synthesis Approach for SoCs. [Citation Graph (, )][DBLP]


  35. Modelling Heterogeneous Embedded Systems in DFCarts. [Citation Graph (, )][DBLP]


  36. SystemJ: A GALS language for system level design. [Citation Graph (, )][DBLP]


  37. A Model Checking Approach to Protocol Conversion. [Citation Graph (, )][DBLP]


  38. STARPro - A new multithreaded direct execution platform for Esterel. [Citation Graph (, )][DBLP]


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