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S. Ramesh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Partha S. Roop, Arcot Sowmya, S. Ramesh
    Automated Component Adaptation by Forced Simulation. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:74-81 [Conf]
  2. Purandar Bhaduri, S. Ramesh
    Synthesis of Synchronous Interfaces. [Citation Graph (0, 0)][DBLP]
    ACSD, 2006, pp:208-216 [Conf]
  3. Sridhar Iyer, S. Ramesh
    A Tool-Suite for Reachability Analysis of Concurrent Object-Oriented Programs. [Citation Graph (0, 0)][DBLP]
    APSEC, 1997, pp:160-0 [Conf]
  4. Partha S. Roop, Arcot Sowmya, S. Ramesh
    A formal approach to component based development of synchronous programs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:421-424 [Conf]
  5. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
    Functional Verification of System on Chips-Practices, Issues and Challenges. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:11-13 [Conf]
  6. S. Ramesh, Purandar Bhaduri
    Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:84-95 [Conf]
  7. S. Ramesh, Sampada Sonalkar, Vijay D'Silva, Naveen Chandra, B. Vijayalakshmi
    A Toolset for Modelling and Verification of GALS Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2004, pp:506-509 [Conf]
  8. Vijay D'Silva, S. Ramesh, Arcot Sowmya
    Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:390-395 [Conf]
  9. Ambar A. Gadkari, S. Ramesh
    Automated Synthesis of Assertion Monitors using Visual Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:390-395 [Conf]
  10. S. Ramesh, S. L. Mehndiratta
    A New Class of High Level Programs for Distributed Computing Systems. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1985, pp:42-72 [Conf]
  11. R. K. Shyamasundar, S. Ramesh
    Languages for Reactive Specifications: Synchrony Vs Asynchrony. [Citation Graph (0, 0)][DBLP]
    FTRTFT, 1994, pp:621-640 [Conf]
  12. Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji
    CESC: a visual formalism for specification and verification of SoCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:354-357 [Conf]
  13. R. K. Shyamasundar, S. Ramesh
    Semantics and Verification of Hierarchical CRP Programs. [Citation Graph (0, 0)][DBLP]
    Hybrid Systems, 1994, pp:436-461 [Conf]
  14. Partha S. Roop, Arcot Sowmya, S. Ramesh
    k-time Forced Simulation: A Formal Verification Technique for IP Reuse. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:50-55 [Conf]
  15. S. Ramesh
    A New Efficient Implementation of CSP with Output Guards. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1987, pp:266-273 [Conf]
  16. Sameer Mahajan, S. Ramesh
    Concurrent Logic Programming and pi Calculus. [Citation Graph (0, 0)][DBLP]
    ICLP, 1997, pp:411- [Conf]
  17. S. Ramesh, R. Lakshmi, R. Govindarajan
    Distributed Shared Memory on IBM SP2. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:338-345 [Conf]
  18. R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh
    A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:193-196 [Conf]
  19. F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh
    Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:119-124 [Conf]
  20. Andres Teene, Bob Davis, R. Castagnetti, J. Brown, S. Ramesh
    Impact of Interconnect Process Variations on Memory Performance and Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:694-699 [Conf]
  21. R. Venkatraman, R. Castagnetti, S. Ramesh
    The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:190-195 [Conf]
  22. Mangala Gowri Nanda, S. Ramesh
    Slicing concurrent programs. [Citation Graph (0, 0)][DBLP]
    ISSTA, 2000, pp:180-190 [Conf]
  23. S. Ramesh, Aditya Rajeev Kulkarni, V. Kamat
    Slicing tools for synchronous reactive programs. [Citation Graph (0, 0)][DBLP]
    ISSTA, 2004, pp:217-220 [Conf]
  24. S. Ramesh
    Fully Abstract Semantics for Higher Order Communicating Systems. [Citation Graph (0, 0)][DBLP]
    MFCS, 1992, pp:463-471 [Conf]
  25. S. Ramesh
    A New and Efficient Implementation of Multiprocess Synchronization. [Citation Graph (0, 0)][DBLP]
    PARLE (2), 1987, pp:387-401 [Conf]
  26. G. Berry, S. Ramesh, R. K. Shyamasundar
    Communicating Reactive Processes. [Citation Graph (0, 0)][DBLP]
    POPL, 1993, pp:85-98 [Conf]
  27. Mangala Gowri Nanda, S. Ramesh
    Pointer Analysis of Multithreaded Java Programs. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:1068-1075 [Conf]
  28. A. Iqbal, A. K. Bhattacharjee, S. D. Dhodapkar, S. Ramesh
    Visual Modeling and Verification of Distributed Reactive Systems. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2003, pp:22-34 [Conf]
  29. Babita Sharma, S. D. Dhodapkar, S. Ramesh
    Assertion Checking Environment (ACE) for Formal Verification of C Programs. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2002, pp:284-295 [Conf]
  30. Aditya Rajeev Kulkarni, S. Ramesh
    Static Slicing of Reactive Programs. [Citation Graph (0, 0)][DBLP]
    SCAM, 2003, pp:98-107 [Conf]
  31. Vijay D'Silva, S. Ramesh, Arcot Sowmya
    Bridge Over Troubled Wrappers: Automated Interface Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:189-194 [Conf]
  32. S. Ramesh
    Efficient Translation of Statecharts to Hardware Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:384-389 [Conf]
  33. Partha S. Roop, Arcot Sowmya, S. Ramesh
    Automatic Component Matching Using Forced Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:64-69 [Conf]
  34. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
    Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:11-13 [Conf]
  35. Purandar Bhaduri, S. Ramesh
    Model Checking of Statechart Models: Survey and Research Directions [Citation Graph (0, 0)][DBLP]
    CoRR, 2004, v:0, n:, pp:- [Journal]
  36. Vinod Ganapathy, S. Ramesh
    Slicing Synchronous Reactive Programs. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2002, v:65, n:5, pp:- [Journal]
  37. R. K. Shyamasundar, S. Ramesh
    Languages for Reactive Specifications: Synchrony Vs Asynchrony. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2000, v:11, n:2, pp:283-314 [Journal]
  38. S. Ramesh
    On the Completeness of Modular Proof Systems. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1990, v:36, n:4, pp:195-201 [Journal]
  39. S. Ramesh, S. L. Mehndiratta
    The Liveness Property of On-the-Fly Garbage Collector - A Proof. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1983, v:17, n:4, pp:189-195 [Journal]
  40. S. Ramesh
    Implementation of communicating reactive processes. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:6, pp:703-727 [Journal]
  41. S. Ramesh, Chandrashekar M. Shetty
    Impossibility of Synchronization in the Presence of Preemption. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1998, v:8, n:1, pp:111-120 [Journal]
  42. Jozef Hooman, S. Ramesh, Willem P. de Roever
    A Compositional Axiomatization of Statecharts. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1992, v:101, n:2, pp:289-335 [Journal]
  43. S. Ramesh, Bommadevara N. Srinivas
    A Direct Characterization of Completion. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1996, v:154, n:2, pp:379-385 [Journal]
  44. Partha S. Roop, Arcot Sowmya, S. Ramesh
    Forced simulation: A technique for automating component reuse in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:602-628 [Journal]
  45. Mangala Gowri Nanda, S. Ramesh
    Interprocedural slicing of multithreaded programs with applications to Java. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2006, v:28, n:6, pp:1088-1144 [Journal]
  46. Sridhar Iyer, S. Ramesh
    Apportioning: A Technique for Efficient Reachability Analysis of Concurrent Object-Oriented Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2001, v:27, n:11, pp:1037-1056 [Journal]
  47. S. Ramesh, S. L. Mehndiratta
    A Methodology for Developing Distributed Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1987, v:13, n:8, pp:967-976 [Journal]
  48. Arcot Sowmya, S. Ramesh
    Extending Statecharts with Temporal Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1998, v:24, n:3, pp:216-231 [Journal]
  49. R. Manoharan, P. Thambidurai, S. Ramesh
    Power aware scalable multicast routing protocol for MANETs. [Citation Graph (0, 0)][DBLP]
    Int. J. Communication Systems, 2006, v:19, n:10, pp:1089-1101 [Journal]
  50. Ajith K. John, Babita Sharma, A. K. Bhattacharjee, S. D. Dhodapkar, S. Ramesh
    Detection of Runtime Errors in MISRA C Programs: A Deductive Approach. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2007, pp:491-504 [Conf]
  51. Manoranjan Satpathy, Michael Butler, Michael Leuschel, S. Ramesh
    Automatic Testing from Formal Specifications. [Citation Graph (0, 0)][DBLP]
    TAP, 2007, pp:95-113 [Conf]
  52. Ambar A. Gadkari, S. Ramesh
    Automated Synthesis of Assertion Monitors using Visual Specifications [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  53. A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. [Citation Graph (, )][DBLP]


  54. Generating and Analyzing Symbolic Traces of Simulink/Stateflow Models. [Citation Graph (, )][DBLP]


  55. AutoMOTGen: Automatic Model Oriented Test Generator for Embedded Control Systems. [Citation Graph (, )][DBLP]


  56. Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. [Citation Graph (, )][DBLP]


  57. A Formal Approach To The Protocol Converter Problem. [Citation Graph (, )][DBLP]


  58. Taming the component timing: A CBD methodology for real-time embedded systems. [Citation Graph (, )][DBLP]


  59. Existential abstractions for distributed reactive systems via syntactic transformations. [Citation Graph (, )][DBLP]


  60. Symbolic analysis for improving simulation coverage of Simulink/Stateflow models. [Citation Graph (, )][DBLP]


  61. Randomized directed testing (REDIRECT) for Simulink/Stateflow models. [Citation Graph (, )][DBLP]


  62. Best Effort Session-Level Congestion Control. [Citation Graph (, )][DBLP]


  63. Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. [Citation Graph (, )][DBLP]


  64. CoGenTe: a tool for code generator testing. [Citation Graph (, )][DBLP]


  65. Conflict-Tolerant Real-Time Features. [Citation Graph (, )][DBLP]


  66. Testing Model-Processing Tools for Embedded Systems. [Citation Graph (, )][DBLP]


  67. Behaviour Directed Testing of Auto-code Generators. [Citation Graph (, )][DBLP]


  68. How to Test Program Generators? A Case Study using flex. [Citation Graph (, )][DBLP]


  69. Test case generation from formal models through abstraction refinement and model checking. [Citation Graph (, )][DBLP]


  70. A Test Bed for Web Services Protocols. [Citation Graph (, )][DBLP]


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