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Chip-Hong Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ravi Kumar Satzoda, Chip-Hong Chang
    VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:693-706 [Conf]
  2. Chip-Hong Chang, Bogdan J. Falkowski
    Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Xiaoyun Deng, Chip-Hong Chang, Erwin Brandle
    A New Method for Eye Extraction from Facial Image. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:29-34 [Conf]
  4. Rui Xiao, Chip-Hong Chang, Thambipillai Srikanthan
    On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:321-325 [Conf]
  5. Zhi Ye, Chip-Hong Chang
    Local Search Method for FIR Filter Coefficients Synthesis. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:255-260 [Conf]
  6. Zhi Ye, Ravi Kumar Satzoda, Udit Sharma, Naveen Nazimudeen, Chip-Hong Chang
    Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:407-409 [Conf]
  7. Jiangmin Gu, Chip-Hong Chang
    Ultra low voltage, low power 4-2 compressor for high speed multiplications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:321-324 [Conf]
  8. Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan
    New efficient residue-to-binary converters for 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup n+1/ - 1}. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:536-539 [Conf]
  9. Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan
    A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:656-659 [Conf]
  10. Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
    Design of a high speed reverse converter for a new 4-moduli set residue number system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:520-523 [Conf]
  11. Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
    A new design method to modulo 2/sup n/-1 squaring. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:664-667 [Conf]
  12. Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan
    A configurable dual moduli multi-operand modulo adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1630-1633 [Conf]
  13. Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar
    A novel multiplexer based truncated array multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:85-88 [Conf]
  14. Chip-Hong Chang, Pengfei Xu
    Frequency sensitive self-organizing maps and its application in color quantization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:804-807 [Conf]
  15. Bogdan J. Falkowski, Chip-Hong Chang
    Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:197-200 [Conf]
  16. Bogdan J. Falkowski, Chip-Hong Chang
    Generation of Multi-Polarity Arithmetic Transform from Reduced Representation of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2168-2171 [Conf]
  17. Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy
    A novel covalent redundant binary Booth encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:69-72 [Conf]
  18. Yu Shao, Chip-Hong Chang
    A versatile speech enhancement system based on perceptual wavelet denoising. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:864-867 [Conf]
  19. Pengfei Xu, Chip-Hong Chang
    Self-organizing topological tree. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:732-735 [Conf]
  20. Menon Shibu, Chip-Hong Chang, Rui Xiao
    FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:452-455 [Conf]
  21. Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
    HWP: a new insight into canonical signed digit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:201-204 [Conf]
  22. Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
    A new contention resolution algorithm for the design of minimal logic depth multiplierless filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:481-484 [Conf]
  23. Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
    I/sup 2/CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1823-1826 [Conf]
  24. Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang
    A novel hybrid pass logic with static CMOS output drive full-adder cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:317-320 [Conf]
  25. Chip-Hong Chang, Bogdan J. Falkowski
    Reed-Muller weight and literal vectors for NPN classification. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:379-382 [Conf]
  26. Bogdan J. Falkowski, Chip-Hong Chang
    Optimization of partially-mixed-polarity Reed-Muller expansions. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:383-386 [Conf]
  27. Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
    Design of residue-to-binary converter for a new 5-moduli superset residue number system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:841-844 [Conf]
  28. Jiangmin Gu, Chip-Hong Chang, Kiat-Seng Yeo
    An interconnect optimized floorplanning of a scalar product macrocell. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:465-468 [Conf]
  29. Zhi-Hui Kong, Kiat-Seng Yeo, Chip-Hong Chang
    An Ultra Low-power Current-mode Sense Amplifier for Sram Applications. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:5, pp:939-952 [Journal]
  30. Bogdan J. Falkowski, Chip-Hong Chang
    Forward and Inverse Transformations Between Haar Spectra and Ordered Binary Decision Diagrams of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:11, pp:1272-1279 [Journal]
  31. Chip-Hong Chang, Zhi Ye, Mingyan Zhang
    Fuzzy-ART based adaptive digital watermarking scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:1, pp:65-81 [Journal]
  32. Pengfei Xu, Chip-Hong Chang, Andrew P. Paplinski
    Self-organizing topological tree for online vector quantization and data clustering. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part B, 2005, v:35, n:3, pp:515-526 [Journal]
  33. Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang
    A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:686-695 [Journal]
  34. Aijiao Cui, Chip-Hong Chang
    Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3687-3690 [Conf]
  35. Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
    A new integrated approach to the design of low-complexity FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. Chip-Hong Chang, Jiajia Chen, A. Prasad Vinod
    Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  37. A. Prasad Vinod, A. Singla, Chip-Hong Chang
    Improved differential coefficients-based low power FIR filters. Part I. Fundamentals. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  38. Yu Shao, Chip-Hong Chang
    A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  39. Yu Shao, Chip-Hong Chang
    A novel hybrid neuro-wavelet system for robust speech recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  40. Yu Shao, Chip-Hong Chang
    A generalized perceptual time-frequency subtraction method for speech enhancement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  41. Yajuan He, Chip-Hong Chang
    A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  42. Ravi Kumar Satzoda, Chip-Hong Chang
    A fast kernel for unifying GF(p) and GF(2m) Montgomery multiplications in a scalable pipelined architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  43. Aijiao Cui, Chip-Hong Chang
    Stego-signature at logic synthesis level for digital design IP protection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  44. Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
    Hamming weight pyramid - A new insight into canonical signed digit representation and its applications. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:3, pp:195-207 [Journal]

  45. Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition. [Citation Graph (, )][DBLP]


  46. An area efficient 64-bit square root carry-select adder for low power applications. [Citation Graph (, )][DBLP]


  47. Intellectual property authentication by watermarking scan chain in design-for-testability flow. [Citation Graph (, )][DBLP]


  48. Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m). [Citation Graph (, )][DBLP]


  49. Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. [Citation Graph (, )][DBLP]


  50. Kernel Extraction for Watermarking Combinational Logic Networks. [Citation Graph (, )][DBLP]


  51. Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. [Citation Graph (, )][DBLP]


  52. A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. [Citation Graph (, )][DBLP]


  53. Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics. [Citation Graph (, )][DBLP]


  54. A Reconfigurable Multi-Modulus Modulo Multiplier. [Citation Graph (, )][DBLP]


  55. Fuzzy-ART based digital watermarking scheme. [Citation Graph (, )][DBLP]


  56. An efficient architecture for adaptive progressive thresholding. [Citation Graph (, )][DBLP]


  57. A MSB-biased self-organizing feature map for still color image compression. [Citation Graph (, )][DBLP]


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