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Jerry L. Trahan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jerry L. Trahan, Michael C. Loui, Vijaya Ramachandran
    Multiplication, Division and Shift Instructions in Parallel Random Access Machines. [Citation Graph (1, 0)][DBLP]
    Theor. Comput. Sci., 1992, v:100, n:1, pp:1-44 [Journal]
  2. Jerry L. Trahan, Michael C. Loui, Vijaya Ramachandran
    The Power of Parallel Random Access Machines with Augmented Instruction Sets. [Citation Graph (0, 0)][DBLP]
    Structure in Complexity Theory Conference, 1989, pp:97-103 [Conf]
  3. Chittur Subbaraman, Jerry L. Trahan, Ramachandran Vaidyanathan
    List Ranking and Graph Algorithms on the Reconfigurable Multiple Bus Machine. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:244-247 [Conf]
  4. Jerry L. Trahan, Ramachandran Vaidyanathan, Chittur Subbaraman
    Constant Time Graph and Poset Algorithms on the Reconfigurable Multiple Bus Machine. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1994, pp:214-217 [Conf]
  5. Anu G. Bourgeois, Jerry L. Trahan
    Fault Tolerant Algorithms for a Linear Array with a Reconfigurable Pipelined Bus System. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:1044-1052 [Conf]
  6. Anu G. Bourgeois, Jerry L. Trahan
    Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:747-752 [Conf]
  7. Hatem M. El-Boghdadi, Ramachandran Vaidyanathan, Jerry L. Trahan, Suresh Rai
    On the Communication Capability of the Self-Reconfigurable Gate Array Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  8. José Alberto Fernández-Zepeda, Ramachandran Vaidyanathan, Jerry L. Trahan
    Improved Scaling Simulation of the General Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:616-624 [Conf]
  9. Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan
    Configuring the Circuit Switched Tree for Multiple Width Communications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  10. Nitin Srivastava, Jerry L. Trahan, Ramachandran Vaidyanathan, Suresh Rai
    Adaptive Image Filtering Using Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:180- [Conf]
  11. Ratnapuri K. Thiruchelvan, Jerry L. Trahan, Ramachandran Vaidyanathan
    On the Power of Segmenting and Fusing Buses. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:79-83 [Conf]
  12. Jerry L. Trahan, Anu G. Bourgeois, Ramachandran Vaidyanathan, Yi Pan
    Optimally Scaling Permutation Routing on Reconfigurable Linear Arrays with Optical Buses. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:233-0 [Conf]
  13. Jerry L. Trahan, Chun-ming Lu, Ramachandran Vaidyanathan
    Integer and Floating Point Matrix-Vector Multiplication on the Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:702-706 [Conf]
  14. Suresh Rai, Jerry L. Trahan, Thomas Smailus
    Processor Allocation in Faulty Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1995-1998 [Conf]
  15. Hatem M. El-Boghdadi, Ramachandran Vaidyanathan, Jerry L. Trahan, Suresh Rai
    Reconfigurable Mesh on the Reconfigurable Tree Array. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1068-1074 [Conf]
  16. Hatem M. El-Boghdadi, Ramachandran Vaidyanathan, Jerry L. Trahan, Suresh Rai
    On Designing Implementable Algorithms for the Linear Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:241-246 [Conf]
  17. Yi Pan, Jerry L. Trahan, Ramachandran Vaidyanathan
    A Scalable and Efficient Algorithm for Computing the City Block Distance Transform on Reconfigurable Meshes. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1997, v:40, n:7, pp:435-440 [Journal]
  18. Jerry L. Trahan, Vijaya Ramachandran, Michael C. Loui
    Parallel Random Access Machines with both Multiplication and Shifts [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1994, v:110, n:1, pp:96-118 [Journal]
  19. Anu G. Bourgeois, Jerry L. Trahan
    Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2000, v:11, n:4, pp:553-571 [Journal]
  20. Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan
    Routing Multiple Width Communications on the Circuit Switched Tree. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2006, v:17, n:2, pp:271-286 [Journal]
  21. Jerry L. Trahan, S. Vedantham
    Analysis of PRAM Instruction Sets from a Log Cost Perspective. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 1994, v:5, n:3/4, pp:231-246 [Journal]
  22. Jerry L. Trahan, Ramachandran Vaidyanathan
    Scaling multiple addition and prefix sums on the reconfigurable mesh. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:82, n:6, pp:277-282 [Journal]
  23. Ramachandran Vaidyanathan, Jerry L. Trahan
    Optimal Simulation of Multidimensional Reconfigurable Meshes by Two-Dimensional Reconfigurable Meshes. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1993, v:47, n:5, pp:267-273 [Journal]
  24. José Alberto Fernández-Zepeda, Ramachandran Vaidyanathan, Jerry L. Trahan
    Using Bus Linearization to Scale the Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2002, v:62, n:4, pp:495-516 [Journal]
  25. Jerry L. Trahan, Anu G. Bourgeois, Yi Pan, Ramachandran Vaidyanathan
    Optimally Scaling Permutation Routing on Reconfigurable Linear Arrays with Optical Buses. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2000, v:60, n:9, pp:1125-1136 [Journal]
  26. Jerry L. Trahan, Ramachandran Vaidyanathan, Chittur Subbaraman
    Constant Time Graph Algorithms on the Reconfigurable Mutliple Buss Machine. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:46, n:1, pp:1-14 [Journal]
  27. Jerry L. Trahan, Ramachandran Vaidyanathan, Ratnapuri K. Thiruchelvan
    On the Power of Segmenting and Fusing Buses. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:34, n:1, pp:82-94 [Journal]
  28. Anu G. Bourgeois, Jerry L. Trahan
    Fault tolerant algorithms for a linear array with a reconfigurable pipelined bus system. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2003, v:18, n:3, pp:139-153 [Journal]
  29. Ramachandran Vaidyanathan, Jerry L. Trahan, Chun-ming Lu
    Degree of scalability: scalable reconfigurable mesh algorithms for multiple addition and matrix-vector multiplication. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2003, v:29, n:1, pp:95-109 [Journal]
  30. Suresh Rai, Jerry L. Trahan
    A Reconfiguration Technique for Fault Tolerance in a Hypercube. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1992, v:2, n:, pp:129-138 [Journal]
  31. Jerry L. Trahan, Hosangadi Bhanukumar
    Parallel Random Access Machines without Boolean Operations. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1994, v:4, n:, pp:117-124 [Journal]
  32. Jerry L. Trahan, Anu G. Bourgeois, Ramachandran Vaidyanathan
    Tighter and Broader Complexity Results for Reconfigurable Models. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1998, v:8, n:3, pp:271-282 [Journal]
  33. José Alberto Fernández-Zepeda, Ramachandran Vaidyanathan, Jerry L. Trahan
    Scaling Simulation of the Fusing-Restricted Reconfigurable Mesh. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:9, pp:861-871 [Journal]
  34. Suresh Rai, Jerry L. Trahan, Thomas Smailus
    Processor Allocation in Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:6, pp:606-616 [Journal]
  35. Sieteng Soh, Suresh Rai, Jerry L. Trahan
    Improved Lower Bounds on the Reliability of Hypercube Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:4, pp:364-378 [Journal]

  36. Scheduling Real Time Tasks on Heterogeneous Reconfigurable Devices. [Citation Graph (, )][DBLP]


  37. Regions Method for Online Placement of Real-Time Tasks on Partially Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  38. Reconfigurable Mesh Techniques and Applications. [Citation Graph (, )][DBLP]


  39. Maximal strips data structure to represent free space on partially reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  40. Secure Referee Selection for Fair and Responsive Peer-to-Peer Gaming. [Citation Graph (, )][DBLP]


  41. ATARIC: an algebraic technique to analyse reconfiguration for fault tolerance in a hypercube. [Citation Graph (, )][DBLP]


  42. Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm. [Citation Graph (, )][DBLP]


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