The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Gordon Steven: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Daniel Tate, Gordon Steven, Fleur Steven
    Static Scheduling for Out-of-order Instruction Issue Processors. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:90-96 [Conf]
  2. Colin Egan, Gordon Steven, Lucian N. Vintan
    Cached Two-Level Adaptive Branch Predictors with Multiple Stages. [Citation Graph (0, 0)][DBLP]
    ARCS, 2002, pp:179-194 [Conf]
  3. Colin Egan, Gordon Steven, Won Shim, Lucian N. Vintan
    Applying Caching to Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:186-193 [Conf]
  4. Roger Collins, Gordon Steven
    Instruction Scheduling for a Superscalar Architecture. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1996, pp:643-650 [Conf]
  5. Daniel Tate, Gordon Steven, Paul Findlay
    The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10325-10328 [Conf]
  6. Colin Egan, Gordon Steven, Patrick Quick, Rubén Anguera, Fleur Steven, Lucian N. Vintan
    Two-level branch prediction using neural networks. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:557-570 [Journal]

Search in 0.024secs, Finished in 0.025secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002