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Douglas L. Maskell: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. K. S. Tham, Douglas L. Maskell
    Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:391-404 [Conf]
  2. Jacop Yanto, Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell
    Biological Sequence Analysis with Hidden Markov Models on an FPGA. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:429-439 [Conf]
  3. Xiaoyong Chen, Douglas L. Maskell
    M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:191-201 [Conf]
  4. Timothy F. Oliver, Douglas L. Maskell
    Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:141-146 [Conf]
  5. Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell
    Hyper customized processors for bio-sequence database scanning on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:229-237 [Conf]
  6. Timothy F. Oliver, Douglas L. Maskell
    An FPGA Model for Developing Dynamic Circuit Computing. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:281-282 [Conf]
  7. Timothy F. Oliver, Bertil Schmidt, Yanto Jakop, Douglas L. Maskell
    Accelerating the Viterbi Algorithm for Profile Hidden Markov Models Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (1), 2006, pp:522-529 [Conf]
  8. Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Darran Nathan, Ralf Clemens
    Multiple Sequence Alignment on an FPGA. [Citation Graph (0, 0)][DBLP]
    ICPADS (2), 2005, pp:326-330 [Conf]
  9. Douglas L. Maskell, Graham S. Woods, Andrew Kerans
    A hardware efficient implementation of an adaptive subsample delay estimator. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:317-320 [Conf]
  10. Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Achutavarrier Prasad Vinod
    A reconfigurable architecture for scanning biosequence databases. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4799-4802 [Conf]
  11. Timothy F. Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, Douglas L. Maskell
    Using reconfigurable hardware to accelerate multiple sequence alignment with ClustalW. [Citation Graph (0, 0)][DBLP]
    Bioinformatics, 2005, v:21, n:16, pp:3431-3432 [Journal]
  12. Jussipekka Leiwo, Lam-for Kwok, Douglas L. Maskell, Nenad Stankovic
    A technique for expressing IT security objectives. [Citation Graph (0, 0)][DBLP]
    Information & Software Technology, 2006, v:48, n:7, pp:532-539 [Journal]
  13. Timothy F. Oliver, Douglas L. Maskell
    Execution Objects for Dynamically Reconfigurable FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  14. K. S. Tham, Douglas L. Maskell
    Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  15. Douglas L. Maskell, Jussipekka Leiwo, Jagdish Chandra Patra
    The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  16. Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong
    C-Based Design Methodology for FPGA Implementation of ClustalW MSA. [Citation Graph (0, 0)][DBLP]
    PRIB, 2007, pp:11-18 [Conf]
  17. Xiaoyong Chen, Douglas L. Maskell
    Supporting multiple-input, multiple-output custom functions in configurable processors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:263-271 [Journal]

  18. A Reconfigurable Bloom Filter Architecture for BLASTN. [Citation Graph (, )][DBLP]


  19. MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA. [Citation Graph (, )][DBLP]


  20. Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. [Citation Graph (, )][DBLP]


  21. A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). [Citation Graph (, )][DBLP]


  22. Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system. [Citation Graph (, )][DBLP]


  23. Workshop on Using Emerging Parallel Architectures for Computational Science. [Citation Graph (, )][DBLP]


  24. An Embedded Systems graduate education for Singapore. [Citation Graph (, )][DBLP]


  25. Parallel reconstruction of neighbor-joining trees for large multiple sequence alignments using CUDA. [Citation Graph (, )][DBLP]


  26. Type-2 GA-TSK fuzzy neural network. [Citation Graph (, )][DBLP]


  27. Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions. [Citation Graph (, )][DBLP]


  28. Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems. [Citation Graph (, )][DBLP]


  29. Multiplierless multi-standard SDR channel filters. [Citation Graph (, )][DBLP]


  30. MSAProbs: multiple sequence alignment based on pair hidden Markov models and partition function posterior probabilities. [Citation Graph (, )][DBLP]


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