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Himanshu Thapliyal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Himanshu Thapliyal, M. B. Srinivas
    A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:805-817 [Conf]
  2. Himanshu Thapliyal, M. B. Srinivas
    The New BCD Subtractor and Its Reversible Logic Implementation. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:466-472 [Conf]
  3. Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture. [Citation Graph (0, 0)][DBLP]
    AMCS, 2005, pp:72-76 [Conf]
  4. Himanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, Hamid R. Arabnia
    Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:130-134 [Conf]
  5. Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    Design for A Fast And Low Power 2's Complement Multiplier. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:165-167 [Conf]
  6. Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia
    Verilog Coding Style for Efficient Synthesis In FPGA. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:85-90 [Conf]
  7. Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
    A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:36-38 [Conf]
  8. Himanshu Thapliyal, Hamid R. Arabnia
    Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:64-69 [Conf]
  9. Himanshu Thapliyal, Hamid R. Arabnia
    A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:70-76 [Conf]
  10. Himanshu Thapliyal, Sumedha K. Gupta
    Design of Novel Reversible Carry Look-Ahead BCD Subtractor. [Citation Graph (0, 0)][DBLP]
    ICIT, 2006, pp:253-258 [Conf]
  11. Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. [Citation Graph (0, 0)][DBLP]
    CSC, 2005, pp:74-77 [Conf]
  12. Himanshu Thapliyal, Hamid R. Arabnia
    High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:413-416 [Conf]
  13. Himanshu Thapliyal, Hamid R. Arabnia
    A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:434-439 [Conf]
  14. Himanshu Thapliyal, Hamid R. Arabnia
    A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:440-446 [Conf]
  15. Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:60-68 [Conf]
  16. Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:106-116 [Conf]
  17. Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    Reversible Logic Synthesis of Half, Full and Parallel Subtractors. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:165-181 [Conf]
  18. Pallavi Devi Gopineedi, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:160-168 [Conf]
  19. Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier. [Citation Graph (0, 0)][DBLP]
    Security and Management, 2005, pp:40-44 [Conf]
  20. Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
    Implementation of A Fast Square In RSA Encryption/Decryption Architecture. [Citation Graph (0, 0)][DBLP]
    Security and Management, 2005, pp:371-374 [Conf]
  21. Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas
    Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:414-417 [Conf]
  22. Vishal Verma, Himanshu Thapliyal
    A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:361-365 [Conf]
  23. Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
    Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:387-392 [Conf]
  24. Himanshu Thapliyal, A. Prasad Vinod
    Designing Efficient Online Testable Reversible Adders With New Reversible Gate. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1085-1088 [Conf]
  25. Himanshu Thapliyal, A. Prasad Vinod
    Design of Reversible Sequential Elements With Feasibility of Transistor Implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:625-628 [Conf]
  26. Himanshu Thapliyal, Mark Zwolinski
    Reversible Logic to Cryptographic Hardware: A New Paradigm [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  27. Himanshu Thapliyal, Hamid R. Arabnia, A. Prasad Vinod
    Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  28. Himanshu Thapliyal, M. B. Srinivas
    Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  29. Himanshu Thapliyal, M. B. Srinivas
    VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  30. Himanshu Thapliyal, Hamid R. Arabnia
    Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  31. Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas
    Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  32. Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
    Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  33. Himanshu Thapliyal, M. B. Srinivas
    A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  34. Himanshu Thapliyal, M. B. Srinivas
    An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  35. Himanshu Thapliyal, M. B. Srinivas
    Novel Reversible Multiplier Architecture Using Reversible TSG Gate [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]

  36. Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. [Citation Graph (, )][DBLP]


  37. Novel Reversible Multiplier Architecture Using Reversible TSG Gate. [Citation Graph (, )][DBLP]


  38. Partial Reversible Gates(PRG) for Reversible BCD Arithmetic. [Citation Graph (, )][DBLP]


  39. Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs. [Citation Graph (, )][DBLP]


  40. Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. [Citation Graph (, )][DBLP]


  41. Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. [Citation Graph (, )][DBLP]


  42. Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures. [Citation Graph (, )][DBLP]


  43. Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs [Citation Graph (, )][DBLP]


  44. Partial Reversible Gates(PRG) for Reversible BCD Arithmetic [Citation Graph (, )][DBLP]


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