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M. B. Srinivas :
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Himanshu Thapliyal , M. B. Srinivas A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:805-817 [Conf ] Himanshu Thapliyal , M. B. Srinivas The New BCD Subtractor and Its Reversible Logic Implementation. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2006, pp:466-472 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture. [Citation Graph (0, 0)][DBLP ] AMCS, 2005, pp:72-76 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Design for A Fast And Low Power 2's Complement Multiplier. [Citation Graph (0, 0)][DBLP ] CDES, 2005, pp:165-167 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Rameshwar Rao , Hamid R. Arabnia Verilog Coding Style for Efficient Synthesis In FPGA. [Citation Graph (0, 0)][DBLP ] CDES, 2005, pp:85-90 [Conf ] Saurabh Kotiyal , Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. [Citation Graph (0, 0)][DBLP ] CSC, 2005, pp:74-77 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor. [Citation Graph (0, 0)][DBLP ] ESA, 2005, pp:60-68 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs. [Citation Graph (0, 0)][DBLP ] ESA, 2005, pp:106-116 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Reversible Logic Synthesis of Half, Full and Parallel Subtractors. [Citation Graph (0, 0)][DBLP ] ESA, 2005, pp:165-181 [Conf ] Pallavi Devi Gopineedi , Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. [Citation Graph (0, 0)][DBLP ] ESA, 2006, pp:160-168 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier. [Citation Graph (0, 0)][DBLP ] Security and Management, 2005, pp:40-44 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Implementation of A Fast Square In RSA Encryption/Decryption Architecture. [Citation Graph (0, 0)][DBLP ] Security and Management, 2005, pp:371-374 [Conf ] K. S. Sainarayanan , J. V. R. Ravindra , M. B. Srinivas Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. [Citation Graph (0, 0)][DBLP ] DELTA, 2006, pp:336-339 [Conf ] Himanshu Thapliyal , Anvesh Ramasahayam , Vivek Reddy Kotha , Kunul Gottimukkula , M. B. Srinivas Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder. [Citation Graph (0, 0)][DBLP ] DELTA, 2006, pp:414-417 [Conf ] Ramachandruni Venkata Kamala , M. Sudhakar , M. B. Srinivas An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). [Citation Graph (0, 0)][DBLP ] DSD, 2006, pp:155-159 [Conf ] Sreehari Veeramachaneni , Lingamneni Avinash , Kirthi M. Krishna , M. B. Srinivas Novel architectures for efficient (m, n) parallel counters. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2007, pp:188-191 [Conf ] Chittarsu Raghunandan , K. S. Sainarayanan , M. B. Srinivas Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2007, pp:371-376 [Conf ] Keerthi Laal Kala , M. B. Srinivas A 32-Bit Binary Floating Point Neuro-Chip. [Citation Graph (0, 0)][DBLP ] ICNC (3), 2005, pp:1015-1021 [Conf ] Sreehari Veeramachaneni , Kirthi M. Krishna , Lingamneni Avinash , Reddy Puppala Sreekanth , M. B. Srinivas Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2007, pp:343-350 [Conf ] K. S. Sainarayanan , Chittarsu Raghunandan , M. B. Srinivas Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2007, pp:401-408 [Conf ] Yaswanth Narvaneni , M. B. Srinivas Local Language Support for Handheld Devices. [Citation Graph (0, 0)][DBLP ] ITCC (2), 2005, pp:799-800 [Conf ] Himanshu Thapliyal , Saurabh Kotiyal , M. B. Srinivas Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:387-392 [Conf ] Sreehari Veeramachaneni , Kirthi M. Krishna , Lingamneni Avinash , Reddy Puppala Sreekanth , M. B. Srinivas Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:324-329 [Conf ] M. Sudhakar , Ramachandruni Venkata Kamala , M. B. Srinivas A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n). [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:750-755 [Conf ] K. S. Sainarayanan , J. V. R. Ravindra , M. B. Srinivas A novel deep submicron low power bus coding technique. [Citation Graph (0, 0)][DBLP ] Circuits, Signals, and Systems, 2005, pp:154-159 [Conf ] Sreehari Veeramachaneni , Kirthi M. Krishna , Lingamneni Avinash , Reddy Puppala Sreekanth , M. B. Srinivas Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:3271-3274 [Conf ] Chittarsu Raghunandan , K. S. Sainarayanan , M. B. Srinivas Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:1129-1132 [Conf ] K. S. Sainarayanan , J. V. R. Ravindra , M. B. Srinivas A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Shashank Mittal , Md. Zafar Ali Khan , M. B. Srinivas A Comparative Study of Different FFT Architectures for Software Defined Radio. [Citation Graph (0, 0)][DBLP ] SAMOS, 2007, pp:375-384 [Conf ] Ramachandruni Venkata Kamala , M. B. Srinivas High-Throughput Montgomery Modular Multiplication. [Citation Graph (0, 0)][DBLP ] VLSI-SoC, 2006, pp:58-62 [Conf ] Keerthi Laal Kala , M. B. Srinivas Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction. [Citation Graph (0, 0)][DBLP ] FOCI, 2007, pp:603-607 [Conf ] Himanshu Thapliyal , M. B. Srinivas Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Himanshu Thapliyal , M. B. Srinivas VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Himanshu Thapliyal , Hamid R. Arabnia , M. B. Srinivas Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Himanshu Thapliyal , Saurabh Kotiyal , M. B. Srinivas Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Himanshu Thapliyal , M. B. Srinivas A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Himanshu Thapliyal , M. B. Srinivas An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Himanshu Thapliyal , M. B. Srinivas Novel Reversible Multiplier Architecture Using Reversible TSG Gate [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. [Citation Graph (, )][DBLP ] Novel Reversible Multiplier Architecture Using Reversible TSG Gate. [Citation Graph (, )][DBLP ] A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. [Citation Graph (, )][DBLP ] Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. [Citation Graph (, )][DBLP ] A low power, variable resolution two-step flash ADC. [Citation Graph (, )][DBLP ] Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. [Citation Graph (, )][DBLP ] A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection. [Citation Graph (, )][DBLP ] A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA. [Citation Graph (, )][DBLP ] Bus encoding schemes for minimizing delay in VLSI interconnects. [Citation Graph (, )][DBLP ] Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks. [Citation Graph (, )][DBLP ] A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. [Citation Graph (, )][DBLP ] A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. [Citation Graph (, )][DBLP ] Design of a Low Power, Variable-Resolution Flash ADC. [Citation Graph (, )][DBLP ] An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. [Citation Graph (, )][DBLP ] Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks. [Citation Graph (, )][DBLP ] Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio. [Citation Graph (, )][DBLP ] A Generic Architecture for Intelligent System Hardware. [Citation Graph (, )][DBLP ] Search in 0.008secs, Finished in 0.287secs