The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Johann Großschädl: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Stefan Tillich, Johann Großschädl
    A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2m). [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:282-295 [Conf]
  2. Johann Großschädl, Guy-Armand Kamendje
    Architectural Enhancements for Montgomery Multiplication on Embedded RISC Processors. [Citation Graph (0, 0)][DBLP]
    ACNS, 2003, pp:418-434 [Conf]
  3. Johann Großschädl
    The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip. [Citation Graph (0, 0)][DBLP]
    ACSAC, 2000, pp:384-393 [Conf]
  4. Johann Großschädl, Guy-Armand Kamendje
    Instruction Set Extension for Fast Elliptic Curve Cryptography over Binary Finite Fields GF(2m). [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:455-0 [Conf]
  5. Johann Großschädl, Sandeep S. Kumar, Christof Paar
    Architectural Support for Arithmetic in Optimal Extension Fields. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:111-124 [Conf]
  6. Johann Großschädl, Alexander Szekely, Stefan Tillich
    The energy cost of cryptographic key establishment in wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ASIACCS, 2007, pp:380-382 [Conf]
  7. Johann Großschädl
    A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m). [Citation Graph (0, 0)][DBLP]
    CHES, 2001, pp:202-219 [Conf]
  8. Johann Großschädl, Roberto Maria Avanzi, Erkay Savas, Stefan Tillich
    Energy-Efficient Software Implementation of Long Integer Modular Arithmetic. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:75-90 [Conf]
  9. Johann Großschädl, Erkay Savas
    Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2m). [Citation Graph (0, 0)][DBLP]
    CHES, 2004, pp:133-147 [Conf]
  10. Johann Großschädl
    High-Speed RSA Hardware Based on Barret's Modular Reduction Method. [Citation Graph (0, 0)][DBLP]
    CHES, 2000, pp:191-203 [Conf]
  11. Stefan Tillich, Johann Großschädl
    Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:270-284 [Conf]
  12. Manuel Koschuch, Joachim Lechner, Andreas Weitzer, Johann Großschädl, Alexander Szekely, Stefan Tillich, Johannes Wolkerstorfer
    Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:430-444 [Conf]
  13. Stefan Tillich, Johann Großschädl, Alexander Szekely
    An Instruction Set Extension for Fast and Memory-Efficient AES Implementation. [Citation Graph (0, 0)][DBLP]
    Communications and Multimedia Security, 2005, pp:11-21 [Conf]
  14. Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma
    Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:218-223 [Conf]
  15. Stefan Tillich, Johann Großschädl
    Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP]
    ICCSA (2), 2005, pp:665-675 [Conf]
  16. Johann Großschädl
    A low-power bit-serial multiplier for finite fields GF(2m). [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:37-40 [Conf]
  17. Johann Großschädl
    A unified radix-4 partial product generator for integers and binary polynomials. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:567-570 [Conf]
  18. Stefan Tillich, Johann Großschädl
    A Survey of Public-Key Cryptography on J2ME-Enabled Mobile Devices. [Citation Graph (0, 0)][DBLP]
    ISCIS, 2004, pp:935-944 [Conf]
  19. Markus Hütter, Johann Großschädl, Guy-Armand Kamendje
    A Versatile and Scalable Digit-Serial/Parallel Multiplier Architecture for Finite Fields GF(2m). [Citation Graph (0, 0)][DBLP]
    ITCC, 2003, pp:692-700 [Conf]
  20. Stefan Tillich, Martin Feldhofer, Johann Großschädl
    Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:457-466 [Conf]
  21. Johann Großschädl
    Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:13-19 [Conf]
  22. Johann Großschädl
    A New Serial/Parallel Architecture for a Low Power Modular Multiplier. [Citation Graph (0, 0)][DBLP]
    SEC, 2000, pp:251-260 [Conf]
  23. Johann Großschädl, Guy-Armand Kamendje
    Optimized RISC Architecture for Multiple-Precision Modular Arithmetic. [Citation Graph (0, 0)][DBLP]
    SPC, 2003, pp:253-270 [Conf]
  24. Johann Großschädl, Guy-Armand Kamendje
    Low-Power Design of a Functional Unit for Arithmetic in Finite Fields GF(p) and GF(2m). [Citation Graph (0, 0)][DBLP]
    WISA, 2003, pp:227-243 [Conf]
  25. Johann Großschädl, Karl C. Posch, Stefan Tillich
    Architectural Enhancements to Support Digital Signal Processing and Public-Key Cryptography. [Citation Graph (0, 0)][DBLP]
    WISES, 2004, pp:129-143 [Conf]
  26. Stefan Tillich, Johann Großschädl
    Power Analysis Resistant AES Implementation with Instruction Set Extensions. [Citation Graph (0, 0)][DBLP]
    CHES, 2007, pp:303-319 [Conf]
  27. Johann Großschädl, Stefan Tillich, Christian Rechberger, Michael Hofmann, Marcel Medwed
    Energy evaluation of software implementations of block ciphers under memory constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1110-1115 [Conf]
  28. Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
    A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:209-214 [Conf]
  29. Tobias Vejda, Dan Page, Johann Großschädl
    Instruction Set Extensions for Pairing-Based Cryptography. [Citation Graph (0, 0)][DBLP]
    Pairing, 2007, pp:208-224 [Conf]
  30. Stefan Tillich, Johann Großschädl
    VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors. [Citation Graph (0, 0)][DBLP]
    WAIFI, 2007, pp:40-54 [Conf]

  31. Workload Characterization of a Lightweight SSL Implementation Resistant to Side-Channel Attacks. [Citation Graph (, )][DBLP]


  32. Non-deterministic processors: FPGA-based analysis of area, performance and security. [Citation Graph (, )][DBLP]


  33. Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography. [Citation Graph (, )][DBLP]


  34. Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. [Citation Graph (, )][DBLP]


  35. Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor. [Citation Graph (, )][DBLP]


  36. Hardware/Software Co-design of Public-Key Cryptography for SSL Protocol Execution in Embedded Systems. [Citation Graph (, )][DBLP]


  37. Side-Channel Analysis of Cryptographic Software via Early-Terminating Multiplications. [Citation Graph (, )][DBLP]


  38. Cryptographic Side-Channels from Low-Power Cache Memory. [Citation Graph (, )][DBLP]


  39. On Software Parallel Implementation of Cryptographic Pairings. [Citation Graph (, )][DBLP]


  40. Energy-Efficient Implementation of ECDH Key Exchange for Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  41. TinySA: a security architecture for wireless sensor networks. [Citation Graph (, )][DBLP]


  42. Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices. [Citation Graph (, )][DBLP]


  43. Reassessing the TCG Specifications for Trusted Computing in Mobile and Embedded Systems. [Citation Graph (, )][DBLP]


  44. Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath. [Citation Graph (, )][DBLP]


  45. Enhancing an Embedded Processor Core with a Cryptographic Unit for Speed and Security. [Citation Graph (, )][DBLP]


Search in 0.181secs, Finished in 0.183secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002