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Kun-Lin Tsai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung
    State Reordering for Low Power Combinational Logic. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:268-276 [Conf]
  2. Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan
    A low power scheduling method using dual V/sub dd/ and dual V/sub th/. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:684-687 [Conf]
  3. Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai
    Synthesis of partition-codec architecture for low power and small area circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:523-526 [Conf]
  4. Po-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai
    An entropy-based algorithm to reduce area overhead for bipartition-codec architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:49-52 [Conf]
  5. Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai
    A bipartition-codec architecture to reduce power in pipelinedcircuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:343-348 [Journal]
  6. Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai
    Bipartitioning and encoding in low-power pipelined circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:24-32 [Journal]
  7. Kun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, Feipei Lai
    Low power scheduling method using multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

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