The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Shanq-Jang Ruan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung
    State Reordering for Low Power Combinational Logic. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:268-276 [Conf]
  2. Shang-Fang Tsai, Shanq-Jang Ruan
    DS2IS: Dictionary-based Segmented Signal Inversion Scheme for Low Power Dynamic Bus Design. [Citation Graph (0, 0)][DBLP]
    ICIT, 2006, pp:293-296 [Conf]
  3. Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang
    A bipartition-codec architecture to reduce power in pipelined circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:84-90 [Conf]
  4. Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan
    Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:334-339 [Conf]
  5. Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai
    Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:327-0 [Conf]
  6. Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn
    Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  7. Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu
    On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:277-280 [Conf]
  8. Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn
    An efficient algorithm for simultaneous wire permutation, inversion, and spacing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:109-112 [Conf]
  9. Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan
    A low power scheduling method using dual V/sub dd/ and dual V/sub th/. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:684-687 [Conf]
  10. Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai
    Synthesis of partition-codec architecture for low power and small area circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:523-526 [Conf]
  11. Po-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai
    An entropy-based algorithm to reduce area overhead for bipartition-codec architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:49-52 [Conf]
  12. Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen
    Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:114-119 [Conf]
  13. Shanq-Jang Ruan, Shang-Fang Tsai, Yu-Ting Pai
    Design and Analysis of Low Power Dynamic Bus Based on RLC simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:113-118 [Conf]
  14. Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan
    An Efficient Two-Level Filter Scheme for Low Power Cache. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:61-66 [Conf]
  15. Yu-Ting Pai, Shanq-Jang Ruan, Jürgen Götze
    Energy-Efficient Watermark Algorithm Based on Pairing Mechanism. [Citation Graph (0, 0)][DBLP]
    KES (1), 2005, pp:1219-1225 [Conf]
  16. Kuen-Pin Wu, Shanq-Jang Ruan, Feipei Lai, Chih-Kuang Tseng
    On Key Distribution in Secure Multicasting. [Citation Graph (0, 0)][DBLP]
    LCN, 2000, pp:208-212 [Conf]
  17. Yu-Ting Pai, Shanq-Jang Ruan, Jürgen Götze
    A High Quality Robust Watermarking Scheme. [Citation Graph (0, 0)][DBLP]
    PCM, 2006, pp:650-657 [Conf]
  18. Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai
    A bipartition-codec architecture to reduce power in pipelinedcircuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:343-348 [Journal]
  19. Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai
    Bipartitioning and encoding in low-power pipelined circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:24-32 [Journal]
  20. Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn
    Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:421-425 [Journal]
  21. Shanq-Jang Ruan, Wei-te Lin
    Bipartition Architecture for Low Power JPEG Huffman Decoder. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:235-243 [Conf]
  22. Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan
    Improve CAM power efficiency using decoupled match line scheme. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:165-170 [Conf]
  23. Kun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, Feipei Lai
    Low power scheduling method using multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  24. Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn
    ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:942-949 [Journal]
  25. Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai
    Design and analysis of low-power cache using two-level filter scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:568-580 [Journal]

  26. Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA. [Citation Graph (, )][DBLP]


  27. Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm. [Citation Graph (, )][DBLP]


  28. A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes. [Citation Graph (, )][DBLP]


  29. A Simple and Accurate Color Face Detection Algorithm in Complex Background. [Citation Graph (, )][DBLP]


  30. An energy efficient and high securitywatermarking mechanism based on DS-CDMA. [Citation Graph (, )][DBLP]


  31. Advanced background subtraction approach using Laplacian distribution model. [Citation Graph (, )][DBLP]


  32. Advanced motion detection for intelligent video surveillance systems. [Citation Graph (, )][DBLP]


  33. Energy analysis of bipartition architecture for pipelined circuits. [Citation Graph (, )][DBLP]


  34. Integrating Bi-Direction Audio and Video Transmission for UltraVNC. [Citation Graph (, )][DBLP]


Search in 0.047secs, Finished in 0.050secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002