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Pedro C. Diniz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Martin C. Rinard, Pedro C. Diniz
    Commutativity Analysis: A New Analysis Framework for Parallelizing Compilers. [Citation Graph (1, 0)][DBLP]
    PLDI, 1996, pp:54-67 [Conf]
  2. Oscar H. Ibarra, Pedro C. Diniz, Martin C. Rinard
    On the Complexity of Commutativity Analysis. [Citation Graph (0, 0)][DBLP]
    COCOON, 1996, pp:323-332 [Conf]
  3. Byoungro So, Pedro C. Diniz, Mary W. Hall
    Using estimates from behavioral synthesis tools in compiler-directed design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:514-519 [Conf]
  4. Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
    Compiler-generated communication for pipelined FPGA applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:610-615 [Conf]
  5. Nastaran Baradaran, Pedro C. Diniz
    A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:6-11 [Conf]
  6. Martin C. Rinard, Pedro C. Diniz
    Semantic Foundations of Commutativity Analysis. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:414-423 [Conf]
  7. Pedro C. Diniz
    Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:73-82 [Conf]
  8. Pedro C. Diniz, Joonseok Park
    Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:91-100 [Conf]
  9. Pedro C. Diniz, Joonseok Park
    Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:207-217 [Conf]
  10. Joonseok Park, Pedro C. Diniz
    Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:297-299 [Conf]
  11. K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz
    Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:296- [Conf]
  12. Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz
    Coarse-Grain Pipelining on Multiple FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:77-0 [Conf]
  13. Pedro C. Diniz, Joonseok Park
    Data reorganization engines for the next generation of system-on-a-chip FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:237-244 [Conf]
  14. Pedro C. Diniz, Joonseok Park
    Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:242- [Conf]
  15. Pablo Moisset, Pedro C. Diniz, Joonseok Park
    Matching and searching analysis for parallel hardware implementation on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:125-133 [Conf]
  16. Nastaran Baradaran, Joonseok Park, Pedro C. Diniz
    Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1113-1115 [Conf]
  17. K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz
    Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:313-323 [Conf]
  18. Nastaran Baradaran, Pedro C. Diniz
    Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:233-240 [Conf]
  19. Pedro C. Diniz
    A Compiler Approach to Performance Prediction Using Empirical-Based Modeling. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science, 2003, pp:916-925 [Conf]
  20. Martin C. Rinard, Pedro C. Diniz
    Eliminating synchronization bottlenecks in object-based programs using adaptive replication. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:83-92 [Conf]
  21. Nastaran Baradaran, Jacqueline Chame, Chun Chen, Pedro C. Diniz, Mary W. Hall, Yoon-Ju Lee, Bing Liu 0002, Robert F. Lucas
    ECO: An Empirical-Based Compilation and Optimization System. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:206- [Conf]
  22. Kiran Bondalapati, Pedro C. Diniz, Phillip Duncan, John J. Granacki, Mary W. Hall, Rajeev Jain, Heidi E. Ziegler
    DEFACTO: A Design Environment for Adaptive Computing Technology. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:570-578 [Conf]
  23. Pedro C. Diniz, Yoon-Ju Lee, Mary W. Hall, Robert F. Lucas
    A Case Study Using Empirical Optimization for a Large, Engineering Application. [Citation Graph (0, 0)][DBLP]
    IPDPS Next Generation Software Program - NSFNGS - PI Workshop, 2004, pp:- [Conf]
  24. Martin C. Rinard, Pedro C. Diniz
    Commutativity Analysis: A Technique for Automatically Parallelizing Pointer-Based Computations. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:14-22 [Conf]
  25. Jacqueline Chame, Chun Chen, Pedro C. Diniz, Mary W. Hall, Yoon-Ju Lee, Robert F. Lucas
    An overview of the ECO project. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  26. Joonseok Park, Pedro C. Diniz
    Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:221-226 [Conf]
  27. Nastaran Baradaran, Pedro C. Diniz, Joonseok Park
    Extending the Applicability of Scalar Replacement to Multiple Induction Variables. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:455-469 [Conf]
  28. Pedro C. Diniz
    Increasing the Accuracy of Shape and Safety Analysis of Pointer-Based Codes. [Citation Graph (0, 0)][DBLP]
    LCPC, 2003, pp:481-494 [Conf]
  29. Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler
    Bridging the Gap between Compilation and Synthesis in the DEFACTO System. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:52-70 [Conf]
  30. Pedro C. Diniz, Bing Liu 0002
    Selector: A Language Construct for Developing Dynamic Applications. [Citation Graph (0, 0)][DBLP]
    LCPC, 2002, pp:218-232 [Conf]
  31. Pedro C. Diniz, Martin C. Rinard
    Lock Coarsening: Eliminating Lock Overhead in Automatically Parallelized Object-Based Programs. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:285-299 [Conf]
  32. Heidi E. Ziegler, Priyadarshini L. Malusare, Pedro C. Diniz
    Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures. [Citation Graph (0, 0)][DBLP]
    LCPC, 2005, pp:62-75 [Conf]
  33. Pedro C. Diniz, Martin C. Rinard
    Dynamic Feedback: An Effective Technique for Adaptive Computing. [Citation Graph (0, 0)][DBLP]
    PLDI, 1997, pp:71-84 [Conf]
  34. Byoungro So, Mary W. Hall, Pedro C. Diniz
    A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems. [Citation Graph (0, 0)][DBLP]
    PLDI, 2002, pp:165-176 [Conf]
  35. Pedro C. Diniz, Martin C. Rinard
    Synchronization Transformations for Parallel Computing. [Citation Graph (0, 0)][DBLP]
    POPL, 1997, pp:187-200 [Conf]
  36. Pedro C. Diniz, Steve Plimpton, Bruce Hendrickson, Robert W. Leland
    Parallel Algorithms for Dynamically Partitioning Unstructured Grids. [Citation Graph (0, 0)][DBLP]
    PPSC, 1995, pp:615-620 [Conf]
  37. Pedro C. Diniz, Tao Yang
    Efficient Parallelization of Relaxation Iterative Methods for Solving Banded Linear Systems on Multiprocessors. [Citation Graph (0, 0)][DBLP]
    PPSC, 1995, pp:490-491 [Conf]
  38. Tao Yang, Pedro C. Diniz, Apostolos Gerasoulis, Vivek Sarkar
    Scheduling Iterative Task Computation on Message-Passing Architectures. [Citation Graph (0, 0)][DBLP]
    PPSC, 1995, pp:581-586 [Conf]
  39. João M. P. Cardoso, Pedro C. Diniz
    Modeling Loop Unrolling: Approaches and Open Issues. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:224-233 [Conf]
  40. Pedro C. Diniz
    Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:213-223 [Conf]
  41. Pedro C. Diniz, Martin C. Rinard
    Synchronization transformations for parallel computing. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1999, v:11, n:13, pp:773-802 [Journal]
  42. Oscar H. Ibarra, Pedro C. Diniz, Martin C. Rinard
    On the Complexity of Commutativity Analysis. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 1997, v:8, n:1, pp:81-0 [Journal]
  43. Yoon-Ju Lee, Pedro C. Diniz, Mary W. Hall, Robert F. Lucas
    Empirical Optimization for a Sparse Linear Solver: A Case Study. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:2-3, pp:165-181 [Journal]
  44. Pedro C. Diniz, Martin C. Rinard
    Lock Coarsening: Eliminating Lock Overhead in Automatically Parallelized Object-Based Programs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1998, v:49, n:2, pp:218-244 [Journal]
  45. Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee
    Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1420-1435 [Journal]
  46. Pedro C. Diniz, Martin C. Rinard
    Eliminating Synchronization Overhead in Automatically Parallelized Programs Using Dynamic Feedback. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1999, v:17, n:2, pp:89-132 [Journal]
  47. Martin C. Rinard, Pedro C. Diniz
    Eliminating synchronization bottlenecks using adaptive replication. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2003, v:25, n:3, pp:316-359 [Journal]
  48. Martin C. Rinard, Pedro C. Diniz
    Commutativity Analysis: A New Analysis Technique for Parallelizing Compilers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1997, v:19, n:6, pp:942-991 [Journal]
  49. Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler
    Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:51-62 [Journal]
  50. Nastaran Baradaran, Pedro C. Diniz
    Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  51. Pedro C. Diniz, Gokul Govindu
    Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  52. Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang
    A Combined Hardware/Software Optimization Framework for Signal Representation and Recognition. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (1), 2007, pp:1230-1237 [Conf]
  53. Joonseok Park, Pedro C. Diniz
    Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:97-109 [Conf]
  54. Nastaran Baradaran, Pedro C. Diniz
    A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  55. Automatic Extraction of Process Control Flow from I/O Operations. [Citation Graph (, )][DBLP]


  56. Introduction. [Citation Graph (, )][DBLP]


  57. High Performance Architectures and Compilers. [Citation Graph (, )][DBLP]


  58. A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops. [Citation Graph (, )][DBLP]


  59. Computation reuse in domain-specific optimization of signal recognition. [Citation Graph (, )][DBLP]


  60. The potential of computation reuse in high-level optimization of a signal recognition system. [Citation Graph (, )][DBLP]


  61. Mobile Context Provider for Social Networking. [Citation Graph (, )][DBLP]


  62. Context Inference for Mobile Applications in the UPCASE Project. [Citation Graph (, )][DBLP]


  63. Guest Editorial. [Citation Graph (, )][DBLP]


  64. Compiling for reconfigurable computing: A survey. [Citation Graph (, )][DBLP]


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